公开(公告)号：WO2018125179A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069368

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： GLASS, Glenn A. ,  PAWASHE, Chytra ,  MURTHY, Anand S. ,  PANTUSO, Daniel ,  GHANI, Tahir

IPC: H01L29/78 ,  H01L29/66

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

公开(公告)号：WO2014204447A1

公开(公告)日：2014-12-24

申请号：PCT/US2013/046400

申请日：2013-06-18

Applicant: INTEL CORPORATION ,  JIANG, Lei ,  RAMAYYA, Edwin B. ,  PANTUSO, Daniel ,  RIOS, Rafael ,  KUHN, Kelin J. ,  KIM, Seiyon

Inventor： JIANG, Lei ,  RAMAYYA, Edwin B. ,  PANTUSO, Daniel ,  RIOS, Rafael ,  KUHN, Kelin J. ,  KIM, Seiyon

IPC: H01L23/34

CPC classification number: H01L23/38 ,  H01L21/8238 ,  H01L27/092 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/181 ,  H05K2201/10166

Abstract: Embodiments of the present disclosure describe techniques and configurations for integrated thermoelectric cooling. In one embodiment, a cooling assembly includes a semiconductor substrate, first circuitry disposed on the semiconductor substrate and configured to generate heat when in operation and second circuitry disposed on the semiconductor substrate and configured to remove the heat by thermoelectric cooling. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于集成热电冷却的技术和配置。 在一个实施例中，冷却组件包括半导体衬底，第一电路设置在半导体衬底上并且被配置为在操作时产生热量，第二电路设置在半导体衬底上并且被配置为通过热电冷却去除热量。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2017111792A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000306

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： MUELLER, Brennen, K. ,  MORROW, Patrick ,  JUN, Kimin ,  FISCHER, Paul, B. ,  PANTUSO, Daniel

IPC: H01L21/768 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L21/76251 ,  H01L21/76838 ,  H01L23/485 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1203 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48105 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2924/014

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more interconnect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

Abstract translation: 包括电路结构的装置，所述电路结构包括器件层; 在器件层的第一侧上的一个或多个导电互连级，并且耦合到晶体管器件中的一些; 以及衬底，所述衬底包括耦合到所述一个或多个导电互连层的导电硅通孔，使得所述一个或多个互连层位于所述硅通孔和所述器件层之间。 一种方法，包括：在衬底上形成多个晶体管器件，所述多个晶体管器件限定器件层; 在所述器件层的第一侧上形成一个或多个互连层; 去除一部分基板; 以及将硅通孔耦合到所述一个或多个互连级，使得所述一个或多个互连级设置在所述器件层和所述硅通孔之间。

公开(公告)号：WO2014120459A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/011858

申请日：2014-01-16

Applicant: INTEL CORPORATION ,  JEZEWSKI, Christopher J. ,  KOBRINSKY, Mauro J. ,  PANTUSO, Daniel ,  BHINGARDE, Siddharth B. ,  O'DAY, Michael P.

Inventor： JEZEWSKI, Christopher J. ,  KOBRINSKY, Mauro J. ,  PANTUSO, Daniel ,  BHINGARDE, Siddharth B. ,  O'DAY, Michael P.

IPC: H01L21/28

CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract translation: 公开了通过增加通孔密度来提高后端互连和其它这种互连结构的抗断裂性的技术和结构。 可以例如在模具内的相邻电路层的填充/加工部分内提供通孔密度的增加。 在一些情况下，上电路层的电隔离（浮置）填充线可以包括在对应于填充线交叉/相交的区域中的下电路层的浮动填充线上的通孔。 在一些这样的情况下，上电路层的浮动填充线可以形成为包括这种通孔的双镶嵌结构。 在一些实施例中，可以在上电路层的浮动填充线和下电路层的充分电隔离的互连线之间提供通孔。 技术/结构可用于为模具提供机械完整性。