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    ERROR CORRECTION IN NON_VOLATILE MEMORY
    1.
    发明申请
    ERROR CORRECTION IN NON_VOLATILE MEMORY 审中-公开
    NON_VOLATILE MEMORY中的错误修正

    公开(公告)号：WO2015047334A1

    公开(公告)日：2015-04-02

    申请号：PCT/US2013/062405

    申请日：2013-09-27

    Applicant: INTEL CORPORATION ,  KWOK, Zion S. ,  MOTWANI, Ravi H. ,  PANGAL, Kiran ,  DAMLE, Prashant S.

    Inventor： KWOK, Zion S. ,  MOTWANI, Ravi H. ,  PANGAL, Kiran ,  DAMLE, Prashant S.

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/108 ,  G06F12/00 ,  G06F2212/7207 ,  G11C29/52 ,  H03M13/1515 ,  H03M13/152

    Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，存储器控制器包括接收对存储在存储器中的数据的读取请求的逻辑，检索数据和至少一个相关联的纠错码字，其中数据和相关联的纠错码字分布在多个存储器件 在存储器中，应用第一纠错程序来解码用数据检索的纠错码字，并响应错误校正码字中的不可校正错误，对存储器中的多个设备应用第二纠错例程。 还公开并要求保护其他实施例。

    ERROR CORRECTION IN MEMORY
    2.
    发明申请
    ERROR CORRECTION IN MEMORY 审中-公开
    内存错误修正

    公开(公告)号：WO2015080819A1

    公开(公告)日：2015-06-04

    申请号：PCT/US2014/061929

    申请日：2014-10-23

    Applicant: INTEL CORPORATION ,  MOTWANI, Ravi H. ,  PANGAL, Kiran

    Inventor： MOTWANI, Ravi H. ,  PANGAL, Kiran

    IPC: G11C29/42 ,  G11C16/06

    CPC classification number: G06F11/1008 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  H03M13/05 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2957

    Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，控制器包括从主机设备接收存储在存储器中的数据的读取请求的逻辑，检索数据和相关联的纠错码字，将数据发送到主机设备，应用纠错例程来解码 使用数据检索的纠错码字，并且响应于纠错码字中的错误，向主机设备发送与该错误相关联的数据的位置。 还公开并要求保护其他实施例。

    MEMORY CONTROLLER WITH DISTRIBUTION TRANSFORMER
    3.
    发明申请
    MEMORY CONTROLLER WITH DISTRIBUTION TRANSFORMER 审中-公开
    带分配变压器的内存控制器

    公开(公告)号：WO2015047239A1

    公开(公告)日：2015-04-02

    申请号：PCT/US2013/061575

    申请日：2013-09-25

    Applicant: INTEL CORPORATION ,  MOTWANI, Ravi H. ,  PANGAL, Kiran

    Inventor： MOTWANI, Ravi H. ,  PANGAL, Kiran

    IPC: G06F12/00

    CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F13/16 ,  G06F13/1694 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069

    Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m and n are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m':n' ratio for bits having the first logic value and bits having the second logic value, where m' and n' are real numbers that are different from one another and respectively differ from m and n. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

    Abstract translation: 描述与存储器的存储器控​​制器相关的方法，装置和系统。 在一个实施例中，存储器控制器可以包括被配置为接收要存储到存储器中的数据的分配变压器，其中所述数据具有用于具有第一逻辑值的位和具有第二逻辑值的位的m1：n1比的分布，其中 m和n是实数。 分配变压器可以将数据变换为偏斜数据，其中偏斜数据对于具有第一逻辑值的位和具有第二逻辑值的位具有m'：n'比的分布，其中m'和n'是实数， 分别不同于m和n。 配电变压器可输出倾斜的数据以存储在存储器中。 可以描述和要求保护其他实施例。

    USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY
    4.
    发明申请
    USE OF ERROR CORRECTION POINTERS TO HANDLE ERRORS IN MEMORY 审中-公开
    使用错误修正指针来处理存储器中的错误

    公开(公告)号：WO2015047228A1

    公开(公告)日：2015-04-02

    申请号：PCT/US2013/061455

    申请日：2013-09-24

    Applicant: INTEL CORPORATION ,  MOTWANI, Ravi H. ,  PANGAL, Kiran

    Inventor： MOTWANI, Ravi H. ,  PANGAL, Kiran

    IPC: G06F11/10 ,  G06F12/00

    CPC classification number: G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1048

    Abstract: Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.

    Abstract translation: 这里描述了使用纠错指针（ECP）来处理存储器中的硬错误的方法，装置和系统。 在实施例中，存储器控制器的读取模块可以读取存储在存储器中的码字。 读取模块可以确定码字中的许多硬错误。 响应于确定硬错误的数量超过阈值，读取模块可以存储与硬错误相关联的ECP信息。 读取模块可以包括用于对码字执行ECC处理的纠错码（ECC）模块。 读取模块可以使用ECP信息来解码码字以响应于ECC过程失败的确定来恢复数据。 可以描述和要求保护其他实施例。

    TECHNIQUES ASSOCIATED WITH PROTECTING SYSTEM CRITICAL DATA WRITTEN TO NON-VOLATILE MEMORY
    5.
    发明申请
    TECHNIQUES ASSOCIATED WITH PROTECTING SYSTEM CRITICAL DATA WRITTEN TO NON-VOLATILE MEMORY 审中-公开
    与保护系统相关的技术关键数据写入非易失性存储器

    公开(公告)号：WO2014051775A1

    公开(公告)日：2014-04-03

    申请号：PCT/US2013/047442

    申请日：2013-06-24

    Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  MOTWANI, Ravi H. ,  DAMLE, Prashant S.

    Inventor： PANGAL, Kiran ,  MOTWANI, Ravi H. ,  DAMLE, Prashant S.

    IPC: G06F12/16 ,  G06F11/10 ,  G11C16/06

    CPC classification number: G06F12/0246 ,  G06F11/1012 ,  G06F12/0238 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/403 ,  G06F2212/7202 ,  G06F2212/7207 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/349

    Abstract: Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed.

    Abstract translation: 公开了与保护写入非易失性存储器的系统关键数据相关的技术的示例。 在一些示例中，可以使用第一数据保护方案将系统关键数据写入非易失性存储器。 包括非系统关键数据的用户数据也可以使用第二数据保护方案写入非易失性存储器。 对于这些示例，两个数据保护方案可以具有相同的给定数据格式大小。 为使用第一数据保护方案提供了各种示例，该方案可以与使用第二数据保护方案提供给用户数据的保护相比提供对系统关键数据的增强保护。 其他的例子被描述和要求保护。

    DYNAMIC WINDOW TO IMPROVE NAND MEMORY ENDURANCE
    6.
    发明申请
    DYNAMIC WINDOW TO IMPROVE NAND MEMORY ENDURANCE 审中-公开
    动态窗口提高NAND存储器的耐用性

    公开(公告)号：WO2013101043A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067810

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  KUMAR, Ravi J.

    Inventor： PANGAL, Kiran ,  KUMAR, Ravi J.

    IPC: G11C16/34 ,  G11C16/10 ,  G11C29/42

    CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

    Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。 在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变 计数值。 或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化 循环计数值。 还公开并要求保护其他实施例。

    TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM
    8.
    发明申请
    TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM 审中-公开
    与两级存储系统的阅读和写入窗口预算相关的技术

    公开(公告)号：WO2014051776A1

    公开(公告)日：2014-04-03

    申请号：PCT/US2013/047453

    申请日：2013-06-25

    Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  DAMLE, Prashant

    Inventor： PANGAL, Kiran ,  DAMLE, Prashant

    IPC: G06F12/02

    CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26

    Abstract: Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed.

    Abstract translation: 公开了与用于二级存储器（2LM）系统的读取和写入窗口预算相关联的技术的示例。 在一些示例中，可以为包括第一级存储器和第二级存储器的2LM系统建立读和写窗口预算。 所建立的读写窗口预算可以包括第一组存储器地址和第二级存储器的第二组存储器地址的组合。 与第二组存储器地址相关联的非易失性存储器单元的单元阈值电压分布相比，第一组存储器地址可以与具有更宽的单元阈值电压分布的非易失性存储单元相关联。 根据一些示例，建立的读和写窗口预算可以是满足给定量的存储器的完成时间阈值和给定量的存储器的可接受的错误率阈值的策略的一部分，当满足对该存储器的读取或写入请求时， 二级内存 其他的例子被描述和要求保护。

    METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES
    9.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES 审中-公开
    改善闪存记忆保护的方法和装置

    公开(公告)号：WO2012074739A1

    公开(公告)日：2012-06-07

    申请号：PCT/US2011/060809

    申请日：2011-11-15

    Applicant: INTEL CORPORATION ,  CHO, Hoon ,  PANGAL, Kiran ,  PARAT, Krishna K. ,  MIELKE, Neal R. ,  KALAVADE, Pranav ,  CHAO, Iwen

    Inventor： CHO, Hoon ,  PANGAL, Kiran ,  PARAT, Krishna K. ,  MIELKE, Neal R. ,  KALAVADE, Pranav ,  CHAO, Iwen

    IPC: G11C16/14 ,  G11C16/06 ,  G11C16/02

    CPC classification number: G11C16/3495 ,  G11C16/02 ,  G11C16/3404

    Abstract: A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program / Erase cycling degradation of the single-level or multi-level cells of the flash memory module.

    Abstract translation: 一种提高闪存耐久性的方法和装置。 在本发明的一个实施例中，高电场被提供给闪速存储器模块的控制门。 施加到闪速存储器模块的高电场消除了控制栅极和闪存模块的有效区域之间的捕获的电荷。 在本发明的一个实施例中，在闪速存储器模块的擦除操作之前，高电场被施加到闪速存储器模块的控制栅极。 通过将高电场施加到闪速存储器模块的控制栅极，本发明的实施例改善了闪存模块的单级或多级单元的编程/擦除循环衰减。

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