公开(公告)号：WO2021159028A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/016964

申请日：2021-02-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： KIM, Youn Cheul ,  CHERNICOFF, Richard S. ,  QUADER, Khandker Nazrul ,  NORMAN, Robert D. ,  YAN, Tianhon ,  SALAHUDDIN, Sayeef ,  HARARI, Eli

IPC: H01L25/00 ,  H01L25/065 ,  G06F3/0611 ,  G06F3/0631 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2225/1047 ,  H01L24/20 ,  H01L25/18 ,  H01L2924/1431 ,  H01L2924/1435

Abstract: A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

公开(公告)号：WO2022126016A2

公开(公告)日：2022-06-16

申请号：PCT/US2021/063094

申请日：2021-12-13

Applicant: QORVO US, INC.

Inventor： COSTA, Julio C. ,  MAXIM, George ,  SCOTT, Baker

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2225/1041 ,  H01L2225/1047 ,  H01L2225/1088 ,  H01L24/10 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2924/10329

Abstract: The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.

公开(公告)号：WO2021252188A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/034194

申请日：2021-05-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FAY, Owen R. ,  RICHARDS, Randon K. ,  LIMAYE, Aparna U. ,  LIM, Dong Soon ,  YOO, Chan H. ,  STREET, Bret K. ,  NAKANO, Eiichi ,  LUO, Shijian

IPC: H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/552 ,  H01L23/66 ,  H01L23/34 ,  H01L25/18 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1047 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5384 ,  H01L24/10 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50

Abstract: Disclosed are microelectronic device assemblies comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device having bond pads operably coupled to conductive traces in contact with the microelectronic devices and extending over a dielectric material to conductive via locations beyond at least one side of the stack for routing power and ground/bias extending through the dielectric materials to contact exposed conductors of the substrate. Data signals are routed between and through microelectronic devices of the stack by structure for data signal communication. Methods of fabrication and related electronic systems are also disclosed.