公开(公告)号：WO2015191238A1

公开(公告)日：2015-12-17

申请号：PCT/US2015/031147

申请日：2015-05-15

Applicant: QUALCOMM INCORPORATED

Inventor： HOLLIS, Timothy Mowry ,  BRUNOLLI, Michael Joseph

IPC: G11C7/10 ,  G06F13/42 ,  H04L25/02 ,  G11C5/06 ,  H03K19/0185 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/02 ,  G11C7/02

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G06F13/4243 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  H03K19/018521 ,  H03K19/018528 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298 ,  Y02D10/14 ,  Y02D10/151

Abstract: A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Abstract translation: 提供源同步系统，其中在数据源端点以及数据宿端点中可能存在非均匀接口。

公开(公告)号：WO2015027022A1

公开(公告)日：2015-02-26

申请号：PCT/US2014/052015

申请日：2014-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： RASOULI, Seid Hadi ,  BRUNOLLI, Michael Joseph ,  HAU-RIEGE, Christine Sung-An ,  MALABRY, Mickael ,  HARISH, Sucheta Kumar ,  BALASUBRAMANIAN, Prathiba ,  MEDISETTI, Kamesh ,  BOMSHTEIN, Nikolay ,  DATTA, Animesh ,  KWON, Ohsang

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L23/482

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract translation: 具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和每个具有NMOS漏极的多个NMOS晶体管包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。 互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。 在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。 互连层上的第三互连件垂直于长度方向延伸，并且从互连组中偏移以将第一互连和第二互连连接在一起。

公开(公告)号：WO2016073119A1

公开(公告)日：2016-05-12

申请号：PCT/US2015/054242

申请日：2015-10-06

Applicant: QUALCOMM INCORPORATED

Inventor： WAYLAND, Mark Charles ,  BRYAN, Thomas Clark ,  HUANG, Yu ,  BRUNOLLI, Michael Joseph

IPC: G11C29/02 ,  H03K3/017

CPC classification number: G11C7/109 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409 ,  H03K3/017 ,  H03K5/1565 ,  H03K19/018507

Abstract: A driver circuit includes an output driver (308) including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster (316) configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module (320) configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.

Abstract translation: 驱动器电路包括包括多个输出驱动器脚的输出驱动器（308）。 驱动器电路还包括配置成调整提供给输出驱动器的信号的占空比的占空比调整器（316）。 驱动器电路还包括隔离模块（320），其被配置为将输出驱动器支路的至少一个输出驱动器支路与输出驱动器支路的剩余输出驱动器支路隔离。 驱动器电路还包括占空比监视器，其被配置为当至少一个输出驱动器支路与剩余的输出驱动器支路隔离时监视至少一个输出驱动器支路的输出，并且将所监视的输出提供给占空比调整器 。

公开(公告)号：WO2015057632A1

公开(公告)日：2015-04-23

申请号：PCT/US2014/060378

申请日：2014-10-14

Applicant: QUALCOMM INCORPORATED

Inventor： BRUNOLLI, Michael Joseph ,  WAYLAND, Mark

IPC: H03K5/06 ,  H03K6/04 ,  H03K17/16 ,  H03K19/00 ,  H03K19/0185 ,  H04L25/02

CPC classification number: H03K19/0005 ,  H03K5/06 ,  H03K6/04 ,  H03K19/017545 ,  H03K19/018528 ,  H04L25/0278 ,  H04L25/05

Abstract: An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths are selectively coupled to the output pad. Each selected calibration path adds a capacitive load to a data node, which affects the slew rate for the data output signal. To adjust the capacitive load on the data node in light of the calibration path selections, the output driver includes a plurality of selectable capacitors corresponding to the plurality of calibration paths. If a calibration path is not selected to couple to the output pad, the corresponding selectable capacitor capacitively loads the data node.

Abstract translation: 用于通过输出焊盘驱动数据输出信号的输出驱动器包括多个校准路径以校准输出焊盘的阻抗。 根据期望的阻抗，各种校准路径选择性地耦合到输出焊盘。 每个选定的校准路径将一个容性负载添加到数据节点，影响数据输出信号的转换速率。 为了根据校准路径选择来调整数据节点上的容性负载，输出驱动器包括对应于多个校准路径的多个可选择的电容器。 如果没有选择校准路径来耦合到输出焊盘，相应的可选择电容可以电容性地加载数据节点。

公开(公告)号：WO2015057627A1

公开(公告)日：2015-04-23

申请号：PCT/US2014/060373

申请日：2014-10-14

Applicant: QUALCOMM INCORPORATED

Inventor： BRUNOLLI, Michael Joseph ,  WAYLAND, Mark

IPC: H03K19/00 ,  G11C7/10 ,  H03K19/003 ,  H04L25/02

CPC classification number: H03K3/01 ,  G11C7/1057 ,  H03K19/0005 ,  H03K19/00315 ,  H04L25/0278

Abstract: An output driver configured to drive an output node includes a pull-down section having a plurality of legs and a pull-up section having a plurality of pull-up legs. Each leg and pull-up leg includes a data path and a calibration path. The data paths in the pull-down section are configured to conduct to ground responsive to an assertion of a complement data output signal whereas the data paths in the pull-up section are configured to conduct to a power supply node responsive to a de-assertion of the complement data output signal.

Abstract translation: 配置为驱动输出节点的输出驱动器包括具有多个支脚的下拉部分和具有多个上拉支腿的上拉部分。 每个腿和上拉腿包括数据路径和校准路径。 下拉部分中的数据路径被配置为响应于补偿数据输出信号的断言而导通到地，而上拉部分中的数据路径被配置为响应于断言而传导到电源节点 的补码数据输出信号。