公开(公告)号：WO2018038855A1

公开(公告)日：2018-03-01

申请号：PCT/US2017/043897

申请日：2017-07-26

Applicant: QUALCOMM INCORPORATED

Inventor： GE, Lixin ,  CHIDAMBARAM, Periannan ,  YANG, Bin ,  LIN, Jiefeng, Jeff ,  NALLAPATI, Giridhar ,  YU, Bo ,  DENG, Jie ,  YUAN, Jun ,  SONG, Stanley, Seungchul

IPC: G01K7/18 ,  H01L23/522

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

Abstract translation: 公开了用于集成电路（IC）中的有源半导体区域的局部温度感测的中线（MOL）金属电阻器温度传感器。 一个或多个金属电阻器被制造在IC中与有源半导体区域相邻的MOL层中以感测相邻有源半导体区域中的环境温度。 金属电阻器的电压将作为金属电阻器的环境温度的函数而改变，其可以被感测以测量与金属电阻器相邻的有源半导体层中的器件周围的环境温度。 通过在MOL层中制造金属电阻器，金属电阻器可以被定位在半导体器件附近并靠近半导体器件，以更准确地感测半导体器件的环境温度。 用于在MOL层中创建触点的相同制造工艺可用于制造金属电阻器。

公开(公告)号：WO2017065921A1

公开(公告)日：2017-04-20

申请号：PCT/US2016/052043

申请日：2016-09-16

Applicant: QUALCOMM INCORPORATED

Inventor： XU, Jeffrey, Junhao ,  SONG, Stanley, Seungchul ,  DU, Yang ,  MACHKAOUTSAN, Vladimir ,  BADAROGLU, Mustafa ,  YEAP, Choh, Fei

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0673 ,  H01L21/02603 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/125 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (CMOS) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion. Furthermore, vertically adjacent nanowires are interconnected at the narrower top end portions and bottom end portions. This allows for connectivity between stacked nanowires and for having separation areas between vertically adjacent heterogeneous nanowires. Having the separation areas allows for gate material to be disposed over a large area of the heterogeneous nanowires and, therefore, provides strong gate control, a shorter nanowire channel structure, low parallel plate parasitic capacitance, and low parasitic channel capacitance. Having the nanowires be heterogeneous, i.e., fabricated using materials of different etching sensitivity, facilitates forming the particular cross section of the nanowires, thus eliminating the use of sacrificial masks/layers to form the heterogeneous nanowires.

Abstract translation: 具体实施方式中公开的方面包括用于互补金属氧化物半导体（CMOS）器件的连续堆叠的异质纳米线的纳米线沟道结构。 每个纳米线具有比中央部分更窄的顶端部分和底端部分。 此外，垂直相邻的纳米线在较窄的顶端部分和底端部分处相互连接。 这允许堆叠的纳米线之间的连接以及垂直相邻的异质纳米线之间的分离区域。 具有分离区域允许将栅极材料设置在大面积的异质纳米线上，并因此提供强大的栅极控制，较短的纳米线沟道结构，低平行板寄生电容和低寄生沟道电容。 使纳米线不均匀，即使用不同蚀刻灵敏度的材料制造，有助于形成纳米线的特定横截面，因此消除了使用牺牲掩模/层来形成异质纳米线。

公开(公告)号：WO2016122882A1

公开(公告)日：2016-08-04

申请号：PCT/US2016/013214

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： LIU, Yanxiang ,  SONG, Stanley, Seungchul

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207 ,  H01L29/0847

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract translation: 半导体器件包括扩散区域，耦合到扩散区域的栅极结构以及耦合到扩散区域的虚拟栅极结构。 栅极结构延伸超过扩散区域的第一距离，并且虚拟栅极结构延伸超过扩散区域的第二距离。

公开(公告)号：WO2014150767A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024174

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley, Seungchul ,  WANG, Zhongze ,  YEAP, Choh fei

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  H01L29/66795

Abstract: Methods for designing fin-based field effect transistors (FinFETs) are disclosed. In one embodiment, an initial FinFET design is evaluated to ascertain the space between fins (i.e., the "fin pitch"). Additionally, the spacing between interconnect metal modules (i.e., the "metal pitch") is ascertained. A ratio of metal pitch to fin pitch is established. From this initial ratio, isotropically scaled sizes are considered along with anisotropically scaled sizes. The variously scaled sizes are compared to design criteria to see what new size best fits the design criteria.

Abstract translation: 公开了用于设计基于鳍的场效应晶体管（FinFET）的方法。 在一个实施例中，评估初始FinFET设计以确定翅片之间的空间（即，“翅片间距”）。 此外，确定互连金属模块之间的间隔（即，“金属间距”）。 确定了金属间距与翅片间距的比率。 从这个初始比例来看，各向异性缩放的尺寸以及各向异性尺寸的尺寸被考虑。 将不同尺寸的尺寸与设计标准进行比较，以了解最符合设计标准的新尺寸。

公开(公告)号：WO2022055598A1

公开(公告)日：2022-03-17

申请号：PCT/US2021/039621

申请日：2021-06-29

Applicant: QUALCOMM INCORPORATED

Inventor： CHAVA, Bharani ,  SONG, Stanley, Seungchul ,  ROY, Abinash ,  KIM, Jonghae

IPC: H01L25/16 ,  H01L25/065 ,  H01L23/528 ,  H01L21/98 ,  H01L25/18

Abstract: An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

公开(公告)号：WO2016148901A1

公开(公告)日：2016-09-22

申请号：PCT/US2016/020211

申请日：2016-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： MOJUMDER, Niladri, Narayan ,  LIU, Ping ,  SONG, Stanley, Seungchul ,  WANG, Zhongze ,  YEAP, Choh, Fei

IPC: G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/02 ,  G11C29/54

CPC classification number: G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

Abstract translation: 所公开的方面包括在多种操作模式下具有基本恒定的操作成品率的静态随机存取存储器（SRAM）阵列。 在一个方面，提供了一种设计具有多种模式操作的SRAM阵列的方法。 该方法包括确定与每个操作模式相关联的性能特征。 配置为在每个操作模式下操作的SRAM位单元被提供给SRAM阵列。 SRAM位单元被偏置以在使用动态自适应辅助技术的操作模式下操作，其中SRAM位单元在整个模式下实现基本上恒定的运行产量。 SRAM位单元具有相应的类型，其中方法中的SRAM位单元类型的数量小于操作模式的数量。 因此，每个SRAM阵列可以实现特定的操作模式，而不需要用于每个模式的单独的SRAM位单元类型，从而降低成本。

公开(公告)号：WO2016089587A1

公开(公告)日：2016-06-09

申请号：PCT/US2015/060912

申请日：2015-11-16

Applicant: QUALCOMM INCORPORATED

Inventor： MOJUMDER, Niladri, Narayan ,  SONG, Stanley, Seungchul ,  WANG, Zhongze ,  RIM, Kern ,  YEAP, Choh, Fei

IPC: H01L27/02 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  H01L27/11

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

Abstract translation: 公开了在单独的金属层上具有字线的静态随机存取存储器（SRAM）位单元，以提高性能。 在一个方面，公开了采用第二金属层中的写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线增加宽度，这降低了字线电阻，减少了访问时间，并提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨迹。 为了将读取的字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在设置在第一金属层中的相应的轨道上。 对应于写入字线的着陆垫被放置在设置在第一金属层中的对应的轨道上。

公开(公告)号：WO2018136168A1

公开(公告)日：2018-07-26

申请号：PCT/US2017/065569

申请日：2017-12-11

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Stanley, Seungchul ,  NALLAPATI, Giridhar ,  CHIDAMBARAM, Periannan

IPC: H01L27/02 ,  G03F1/70 ,  H01L21/033 ,  H01L21/308 ,  H01L27/118

Abstract: Aspects describing modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area are disclosed. In one aspect, a modified SAQP process includes disposing multiple mandrels. First spacers are disposed on either side of each mandrel, and second spacers are disposed on either side of each first spacer. A cut pattern mask is disposed over the second spacers and includes openings that expose second spacers corresponding to locations in which voltage rails are to be disposed. The voltage rails are formed by removing the second spacers exposed by the openings in the cut pattern mask, and disposing the voltage rails in the corresponding locations left vacant by removing the second spacers. Routing lines are disposed over routing tracks formed between each set of the remaining second spacers to allow for interconnecting of active devices formed in the IC cell.

公开(公告)号：WO2016039970A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/046522

申请日：2015-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： ZHU, John, Jianhong ,  RIM, Kern ,  SONG, Stanley, Seungchul ,  XU, Jeffrey, Junhao

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Tie-off structures for middle-of-line (MOL) manufactured integrated circuits, and related methods are disclosed. As a non-limiting example, the tie-off structure may be used to tie-off a drain or source of a transistor to the gate of the transistor, such as provided in a dummy gate used for isolation purposes. In this regard in one aspect, a MOL stack is provided that includes a metal gate connection that is coupled to a metal layer through metal structure disposed in and above a dielectric layer above a gate associated with the metal gate connection. By coupling the metal gate connection to the metal layer, the gate of a transistor may be coupled or "tied-off" to a source or drain element of the transistor. This may avoid the need to etch the metal gate connection provided below the dielectric layer to provide sufficient connectivity between the metal layer and the metal gate connection.

Abstract translation: 公布了中线（MOL）制造集成电路的结合结构及相关方法。 作为非限制性示例，可以使用结合结构将晶体管的漏极或源极结合到晶体管的栅极，例如在用于隔离目的的虚拟栅极中提供。 在这方面，在一方面，提供了一种MOL堆叠，其包括金属栅极连接，金属栅极连接通过设置在与金属栅极连接相关联的栅极上方的电介质层中和上方的金属结构耦合到金属层。 通过将金属栅极连接耦合到金属层，晶体管的栅极可以耦合或“截止”到晶体管的源极或漏极元件。 这可以避免需要蚀刻在介电层下方提供的金属栅极连接，以在金属层和金属栅极连接之间提供足够的连通性。

公开(公告)号：WO2016039968A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/046518

申请日：2015-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： ZHU, John, Jianhong ,  RIM, Kern ,  SONG, Stanley, Seungchul ,  XU, Jeffrey, Junhao ,  YANG, Da

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/53257 ,  H01L21/0217 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

Abstract translation: 公开了采用使用细长通孔的金属线的局部互连的中线（MOL）制造的集成电路（IC）。 还公开了相关方法。 特别地，金属层中的不同金属线可能需要在IC的MOL工艺期间电连接。 在这方面，为了允许金属线互连，而不在例如在示例性方面中在印刷过程中难以提供的金属线上方提供这样的互连，在一个或多个金属线中提供细长或扩张的通孔 IC中的MOL层。 细长通道设置在MOL层中的金属层下方的MOL层中，并且延伸穿过MOL层的金属层中的两个或更多个相邻的金属层。 移动MOL层上方的互连可以简化IC的制造，特别是在纳米（nm）节点尺寸较小的情况下。