公开(公告)号：WO2005072329A2

公开(公告)日：2005-08-11

申请号：PCT/US2005002301

申请日：2005-01-25

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  PEREGO RICHARD E ,  HAMPEL CRAIG E

Inventor： WARE FREDERICK A ,  PEREGO RICHARD E ,  HAMPEL CRAIG E

IPC: H04B1/38 ,  H04L1/24 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04L1/242 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/0292 ,  H04L25/12 ,  H04L27/00

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Abstract translation: 方法和系统提供在通信信道的正常操作期间不时地执行校准周期。 校准周期包括将来自发射机的正常数据源解耦，并在其位置提供校准模式。 使用第二组件上的接收器从通信链路接收校准模式。 响应于所接收的校准模式来确定通信信道的参数的校准值。 校准周期中涉及的步骤可以重新排序以考虑通信信道的利用模式。 对于双向链路，执行校准周期，其包括将接收到的校准模式存储在第二组件上的步骤，以及将这些校准模式重新发送回第一组件以用于调整第一组件上的通道的参数。

公开(公告)号：WO2010117535A3

公开(公告)日：2011-02-03

申请号：PCT/US2010026757

申请日：2010-03-10

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

Inventor： WARE FREDERICK A ,  BROOKS JOHN WELSFORD ,  KASAMSETTY KISHORE VEN ,  PEREGO RICHARD E

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02

CPC classification number: G06F13/161

Abstract: The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.

Abstract translation: 本实施例提供一种存储器系统，其被配置为从存储器控制器向存储器件发送请求，其中该请求包括独立的激活和预充电命令。 activate命令与一个行地址相关联，该地址标识了activate命令的第一行。 响应于激活命令，系统激活存储器设备中第一组中的第一行。 类似地，响应于预充电命令，系统对存储器件中的第二存储体进行预充电。

公开(公告)号：WO2008127698A3

公开(公告)日：2009-03-26

申请号：PCT/US2008004790

申请日：2008-04-11

Applicant: RAMBUS INC ,  PEREGO RICHARD E ,  WARE FREDERICK A

Inventor： PEREGO RICHARD E ,  WARE FREDERICK A

IPC: G11C5/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract translation: 存储器系统包括具有多个存储器 - 控制器块的存储器控​​制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

公开(公告)号：WO2004034401A3

公开(公告)日：2005-03-03

申请号：PCT/US0332205

申请日：2003-10-09

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  PEREGO RICHARD E

Inventor： WARE FREDERICK A ,  PEREGO RICHARD E

IPC: G06F3/00 ,  G06F3/05 ,  G06F3/06 ,  G06F5/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G11C20060101 ,  G11C11/406

CPC classification number: G11C11/406 ,  G06F12/00 ,  G06F13/1605 ,  G11C11/40603

Abstract: Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract translation: 描述了执行重叠刷新和数据访问（读或写）事务的动态存储器系统，其最小化刷新事务对存储器性能的影响。 存储器系统支持针对不同银行的独立且同时的激活和预充电操作。 两组地址寄存器使系统能够同时指定用于刷新和数据访问事务的不同库。

公开(公告)号：WO2005072299A3

公开(公告)日：2006-11-02

申请号：PCT/US2005002139

申请日：2005-01-25

Applicant: RAMBUS INC ,  HAMPEL CRAIG E ,  WARE FREDERICK A ,  PEREGO RICHARD E

Inventor： HAMPEL CRAIG E ,  WARE FREDERICK A ,  PEREGO RICHARD E

IPC: H04B1/38 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04B17/11 ,  H04B17/00 ,  H04B17/21 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/043 ,  H04L7/10 ,  H04L27/00

Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 N -1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Abstract translation: 一种提供执行第一校准序列的方法和系统，例如在系统初始化时建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或具有长度为2比特比特的伪随机比特序列 ，其中N等于或大于7，而第二校准序列使用短校准模式，例如小于16字节的固定代码，并且例如短至​​2字节长。

公开(公告)号：WO2013020105A3

公开(公告)日：2013-05-02

申请号：PCT/US2012049633

申请日：2012-08-03

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  ARYANFAR FARSHID ,  BROOKS JOHN WELSFORD

Inventor： WARE FREDERICK A ,  ARYANFAR FARSHID ,  BROOKS JOHN WELSFORD

IPC: G01S1/02 ,  G01S5/02

CPC classification number: G01S13/84 ,  G01S5/0294 ,  G01S5/06 ,  G01S7/52004 ,  G01S13/878 ,  G01S2007/4091

Abstract: A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.

Abstract translation: 公开了一种关于第一电子设备跟踪第二电子设备的方法。 该方法包括沿着与第一设备相关联的第一固定路径传送第一频率的第一波形。 具有基于第一频率的频率的第二波形沿着第一无线路径从第一设备无线传输到第二设备。 沿着第二无线路径将第二波形从第二设备无线传输到第一设备。 第一和第二波形在相位比较器电路处被接收。 然后将所接收的第一波形的第一相位关系与所接收的重传波形的第二相位关系进行比较。 基于比较关于参考坐标来确定第二设备的坐标。

公开(公告)号：WO2013009442A3

公开(公告)日：2013-03-14

申请号：PCT/US2012043258

申请日：2012-06-20

Applicant: RAMBUS INC ,  WARE FREDERICK A

Inventor： WARE FREDERICK A

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract translation: 设备间信息传输的带宽会动态改变，以适应系统中采用的功率模式之间的转换。 通过选择性地启用和禁用携带信息的单独控制链路和数据链路来改变带宽。 在系统的最高带宽模式期间，所有的数据和控制链路都能够在整个过程中提供最大的信息。 在系统的一个或多个较低带宽模式期间，禁用至少一个数据链路和/或至少一个控制链路以降低设备的功耗。 在每个低带宽模式期间保持启用至少一个数据链路和至少一个控制链路。 对于这些链路，相同的信令速率用于两种带宽模式，以减少否则将由信令速率改变引起的延迟。 此外，还会为禁用的链接生成校准信息，以便这些链接可以快速重新投入使用。

公开(公告)号：WO2012021380A2

公开(公告)日：2012-02-16

申请号：PCT/US2011046669

申请日：2011-08-04

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  ZERBE JARED L ,  LEIBOWITZ BRIAN S

Inventor： WARE FREDERICK A ,  ZERBE JARED L ,  LEIBOWITZ BRIAN S

IPC: G11C7/22 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.

Abstract translation: 当存储器系统进入低功率状态并且需要大量时间以适当的频率重新建立时，用于对高速数据和命令信令链路上的数据和命令传输进行计时的一个或多个定时信号被暂停或以其他方式禁用和/或 阶段，因为系统返回到活动的操作状态。 代替在开始存储器访问操作之前等待高速定时信号被重新建立，替代的较低频率的定时源被用于通过数据和命令信令的组合来定时传送一个或多个存储器访问命令 而高速定时信号正在恢复，从而加快了对存储器设备的存储器访问命令的传输，并减少了退出低功耗状态所需的增量等待时间。 也可以（或者替代地）提供能够在两个或更多个振荡频率之间无故障地移位定时信号的定时信号发生器，从而使得不同频率定时信号能够在任一操作状态下经由相同定时信号路径被传送到系统组件。 当使用定时信号来对通过信息承载的信令链路进行数据（或命令）传输时，无信号地改变定时信号频率的能力使信息承载信令链路上的较低和较高数据速率之间的相应无毛刺移位成为可能。

公开(公告)号：WO2010098901A3

公开(公告)日：2010-10-21

申请号：PCT/US2010021024

申请日：2010-01-14

Applicant: RAMBUS INC ,  WARE FREDERICK A

Inventor： WARE FREDERICK A

IPC: H03K19/0175 ,  H04L25/02

CPC classification number: H03K19/017581 ,  H03K19/017509 ,  H04L25/0272

Abstract: A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel.

Abstract translation: 源终端发射机通过短信道传送数字信号作为每个符号转换的电平之间转换的电压信号。 发射机通过向通道发出充电脉冲来产生每个转换，从而产生一系列充电脉冲。 每单位时间的充电脉冲数与信号的转换密度成比例，因为在相似符号之间不需要电荷脉冲。 因此，用于传送脉冲的电源电流取决于数据模式。 这种数据依赖性可能会导致电源波动，从而导致错误，从而降低性能。 发射机为每个相邻的相似符号对发出合成充电脉冲，以减少电源电流的数据依赖性。 可以缩放合成脉冲以匹配给定通道上符号转换所需的电荷。

公开(公告)号：WO2008130703A8

公开(公告)日：2009-11-26

申请号：PCT/US2008005135

申请日：2008-04-18

Applicant: RAMBUS INC ,  KIZER JADE M ,  WILSON JOHN M ,  EBLE JOHN III ,  WARE FREDERICK A

Inventor： KIZER JADE M ,  WILSON JOHN M ,  EBLE JOHN III ,  WARE FREDERICK A

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

Abstract: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on ' the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

Abstract translation: 用于同步选通存储器系统10的系统和方法。在存储器读取和/或存储器写入操作期间，根据本地时钟信号71/73在数据目的地50/55处对相应的数据选通进行采样。 基于“采样结果，数据选通和本地时钟信号同步。 以这种方式，数据与本地时钟信号同步，使得可以根据本地时钟信号而不是数据选通来执行数据目的地的数据采样。