公开(公告)号：WO2011139496A3

公开(公告)日：2012-01-26

申请号：PCT/US2011032197

申请日：2011-04-13

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  TSERN ELY ,  VOGELSANG THOMAS

Inventor： WARE FREDERICK A ,  TSERN ELY ,  VOGELSANG THOMAS

IPC: H01L23/52 ,  H01L23/538

CPC classification number: H01L23/481 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F2213/0038 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06544 ,  H01L2924/014

Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.

Abstract translation: 集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。 集成电路还包括位于连续区域外部的核心电路。 核心电路耦合到至少一个连接位置。

公开(公告)号：WO2011062825A2

公开(公告)日：2011-05-26

申请号：PCT/US2010056217

申请日：2010-11-10

Applicant: RAMBUS INC ,  WARE FREDERICK A ,  TSERN ELY ,  VOGELSANG THOMAS

Inventor： WARE FREDERICK A ,  TSERN ELY ,  VOGELSANG THOMAS

IPC: G11C29/42 ,  G06F11/10 ,  G11C11/40 ,  G11C29/18

CPC classification number: G11C29/50016 ,  G06F11/1064 ,  G11C11/401 ,  G11C29/808

Abstract: The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

Abstract translation: 所公开的实施例提供了一种动态存储器设备，其包括一组动态存储器单元和一组替代动态存储器单元。 替换动态存储单元组包括包含用于动态存储单元组中的预定故障单元的替换数据位的数据单元以及包含识别故障单元的地址位的地址单元，其中每个数据单元与一组地址 这些单元识别该组动态存储器单元中的相关故障单元。 动态存储设备还包括重新映射电路，其将动态存储单元组中的故障单元重新映射到替换单元组中的相关替换单元。

公开(公告)号：WO2004077524A3

公开(公告)日：2005-10-27

申请号：PCT/US2004005620

申请日：2004-02-25

Applicant: RAMBUS INC ,  WARE FREDERICK ,  BEST SCOTT ,  CHANG TIMOTHY ,  PEREGO RICHARD ,  TSERN ELY ,  MITCHELL JEFF

Inventor： WARE FREDERICK ,  BEST SCOTT ,  CHANG TIMOTHY ,  PEREGO RICHARD ,  TSERN ELY ,  MITCHELL JEFF

IPC: G01R31/317 ,  G06F11/24 ,  H01L21/44

CPC classification number: G11C29/56004 ,  G01R31/31707 ,  G06F11/24 ,  G11C2029/5602

Abstract: A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

Abstract translation: 提供了用于测试和表征电路的方法和装置。 在一个实施例中，半导体部件的高速接口包括高速测试电路。 高速测试电路无需外部高速测试系统进行测试和表征。 在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。 在一个实施例中，包括测试电路的接口可以测试自身或另一接口。 在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。 测试可以在晶片级，元件级和系统中执行。

公开(公告)号：WO2011041058A3

公开(公告)日：2011-07-14

申请号：PCT/US2010047242

申请日：2010-08-31

Applicant: RAMBUS INC ,  LI ADAM H ,  CHEN NING NICHOLAS ,  TSERN ELY ,  FARMWALD MICHAEL

Inventor： LI ADAM H ,  CHEN NING NICHOLAS ,  TSERN ELY ,  FARMWALD MICHAEL

IPC: H04L12/66 ,  H04L9/32 ,  H04W4/24

CPC classification number: H04W12/06 ,  H04L63/0815 ,  H04L63/0892 ,  H04W40/02 ,  H04W88/06

Abstract: Described are methods, devices, and systems to provide enhanced wireless coverage for wireless mobile stations by facilitating centralized authentication for a variety of unrelated networks. The mobile stations can then access Internet and telephony resources via the various networks for improved coverage and bandwidth. Some embodiments support the extension of network coverage using wireless-access points that can be partitioned into multiple virtual access points, one associated with an enterprise and another with an overlay network that facilitates mobile communication over multiple networks. One physical access point can support an enterprise network using one virtual access point and the overlay network using another. Users unaffiliated with an enterprise can access the overlay network via the enterprise's physical access point without gaining access to the enterprise network.

Abstract translation: 描述了通过促进各种不相关网络的集中认证来为无线移动站提供增强的无线覆盖的方法，设备和系统。 然后，移动台可以经由各种网络访问因特网和电话资源，以改善覆盖和带宽。 一些实施例支持使用可以被划分成多个虚拟接入点的无线接入点来扩展网络覆盖范围，一个与企业相关联，另一个具有促进多个网络上的移动通信的覆盖网络。 一个物理接入点可以使用一个虚拟接入点和使用另一个的覆盖网络来支持企业网络。 与企业无关的用户可以通过企业的物理接入点访问覆盖网络，无需访问企业网络。

公开(公告)号：WO2010083006A3

公开(公告)日：2010-10-21

申请号：PCT/US2009068802

申请日：2009-12-18

Applicant: RAMBUS INC ,  BEST SCOTT ,  BRONNER GARY ,  TSERN ELY

Inventor： BEST SCOTT ,  BRONNER GARY ,  TSERN ELY

IPC: H04W88/02 ,  H04W24/10 ,  H04W64/00

CPC classification number: H04W36/385 ,  G01T7/00 ,  H04M2250/12

Abstract: Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone- specific error data can serve as user-specific dosimeters.

Abstract translation: 描述的是携带使用常用半导体存储器形成的辐射探测器的移动电话。 辐射探测器对常规电话中可用的几乎没有额外的硬件，因此可以以少量的费用或包装修改来集成。 低成本支持检测器的广泛分布。 从装有探测器的手机的星座收集的数据可用于定位错误或被盗的核材料或其他潜在危险的辐射源。 电话用户可以收到附近的辐射危险警报，并且聚合的手机特定的错误数据可以用作用户特定的剂量计。

公开(公告)号：WO2007038225A3

公开(公告)日：2007-06-14

申请号：PCT/US2006036894

申请日：2006-09-21

Applicant: RAMBUS INC ,  TSERN ELY

Inventor： TSERN ELY

IPC: G11C5/00

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/04 ,  G11C11/4093 ,  G11C2029/4402 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15182 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of "data slices" or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.

Abstract translation: 存储器模块包括多个信号路径，其从接收来自相关联的多个集成电路存储器件的数据的多个相应的集成电路缓冲器件向存储器模块连接器接口提供数据。 存储器模块形成耦合到各个集成电路缓冲器件的多个“数据片”或存储器模块数据总线的多个部分。 每个集成电路缓冲器件还耦合到总线，该总线提供指定访问至少一个集成电路存储器件的控制信息。 根据实施例，SPD设备存储关于存储器模块的配置信息的信息。 在实施例中，至少一个集成电路缓冲器设备访问存储在SPD设备中的信息。 在封装实施例中，封装容纳集成电路缓冲管芯和多个集成电路存储器管芯。

公开(公告)号：WO2016145328A3

公开(公告)日：2016-11-03

申请号：PCT/US2016022046

申请日：2016-03-11

Applicant: RAMBUS INC

Inventor： WARE FREDERICK ,  TSERN ELY ,  LINSTADT JOHN

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G11C5/063 ,  G11C5/04

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

Abstract translation: 公开了存储器控制器，设备，模块，系统和相关联的方法。 在一个实施例中，存储器模块包括用于经由总线耦合到存储器控制器的引脚接口。 该模块包括至少两个非易失性存储器件，以及设置在引脚接口和至少两个非易失性存储器件之间的缓冲器。 缓冲器从存储器控制器接收与DRAM存储器模块访问命令交错的非易失性存储器访问命令。

公开(公告)号：WO0186455A3

公开(公告)日：2003-01-16

申请号：PCT/US0115413

申请日：2001-05-10

Applicant: RAMBUS INC

Inventor： PERINO DONALD V ,  HABA BELGACEM ,  KHALILI SAYEH ,  PEREGO RICHARD E ,  NGUYEN DAVID ,  GARRETT BILLY W JR ,  TSERN ELY ,  HAMPEL CRAIG E ,  YIP WAI-YEUNG ,  KOLLIPARA RAVINDRAN T

IPC: G06F13/40 ,  H05K1/02 ,  H05K1/14 ,  G06F13/42

CPC classification number: H05K1/147 ,  G06F13/409 ,  H05K1/023 ,  H05K1/148 ,  H05K2201/10189

Abstract: Various module structures are disclosed which may be used to implement modules having (1) to (N) channels. Bus systems may be formed by the interconnection of such modules.

Abstract translation: 公开了可用于实现具有（1）至（N）个通道的模块的各种模块结构。 总线系统可以通过这种模块的互连形成。

公开(公告)号：WO2015126518A3

公开(公告)日：2015-11-12

申请号：PCT/US2014071597

申请日：2014-12-19

Applicant: RAMBUS INC

Inventor： WARE FREDERICK A ,  TRINGALI J JAMES ,  TSERN ELY

IPC: G06F13/14 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84 ,  G11C7/20 ,  G11C14/0018

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory, wherein the first memory device is volatile memory and the second memory device is non-volatile memory; and a control element coupled to the first memory device and the second memory device, the control element to: capture a base image of data stored in the first memory device; store the base image of data in the second memory device; capture incremental updates to the data stored in the first memory device; update the base image stored in the second memory device with the incremental updates; and in response to loss of power to the non-volatile memory module, restore the base image and any incremental updates to the first memory device.

Abstract translation: 本文描述的实施例描述了用于在易失性存储器和非易失性存储器中包括两个或多个存储器技术的多层存储器系统中的非易失性存储器持久性的技术，其中第一存储器件是易失性存储器，而第二存储器件是非易失性存储器， 易失性记忆 以及耦合到所述第一存储器设备和所述第二存储器设备的控制元件，所述控制元件用于：捕获存储在所述第一存储器设备中的数据的基本映像; 将数据的基本图像存储在第二存储器件中; 捕获存储在第一存储设备中的数据的增量更新; 用增量更新更新存储在第二存储设备中的基本图像; 并且响应于对所述非易失性存储器模块的电力的损失，恢复所述基本映像和对所述第一存储器设备的任何增量更新。