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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：WO2010038630A1

    公开(公告)日：2010-04-08

    申请号：PCT/JP2009/066321

    申请日：2009-09-11

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  OHMARU, Takuro ,  ATSUMI, Tomoaki ,  SAITO, Toshihiko

    Inventor： OHMARU, Takuro ,  ATSUMI, Tomoaki ,  SAITO, Toshihiko

    IPC: G11C29/04

    CPC classification number: G11C29/44 ,  G11C16/3459 ,  G11C16/349 ,  G11C29/4401 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402

    Abstract: Easy and fast memory access with correcting defects is to be realized. In a spare memory in a semiconductor memory device, a redundant memory cell array that stores the number of correcting defects is provided. When a signal from the outside is received, the signal is switched to the redundant memory cell array, and the number of correcting defects is judged. Then, based on the result of the judgment, it is determined the judgment of a defective memory cell is continued or the judgment is finished to write data to a main memory cell. By providing the redundant memory cell array that stores the number of correcting defects, a state of correcting defects can be observed fast in such a manner.

    Abstract translation: 要实现具有纠正缺陷的简单快速的存储器访问。 在半导体存储器件的备用存储器中，提供存储修正缺陷数量的冗余存储单元阵列。 当接收到来自外部的信号时，信号被切换到冗余存储单元阵列，并且判断校正缺陷的数量。 然后，基于判断结果，确定不良存储单元的判断继续，或判断结束，将数据写入主存储单元。 通过提供存储校正缺陷数量的冗余存储单元阵列，可以以这种方式快速地观察校正缺陷的状态。

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 审中-公开
    半导体器件和电子器件

    公开(公告)号：WO2017055967A1

    公开(公告)日：2017-04-06

    申请号：PCT/IB2016/055614

    申请日：2016-09-21

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： OHMARU, Takuro ,  MAEHASHI, Yukio

    IPC: G11C11/4097 ,  G11C14/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L27/14 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/14616 ,  H01L27/14636 ,  H01L29/24 ,  H01L29/7869 ,  H04N5/378

    Abstract: A small semiconductor device suitable for high-speed operation is provided. The semiconductor device includes a first circuit, a global bit line pair for writing, a global bit line pair for reading, and a local bit line pair. The first circuit includes second to fifth circuits. The second to fifth circuits are electrically connected to each other by the local bit line pair. The second circuit functions as a read/write selection switch. The third circuit functions as a working memory that stores 1-bit complementary data temporarily. The fourth circuit has a function of precharging the local bit line pair. The fifth circuit includes n (n is an integer of 2 or more) sixth circuits. The sixth circuits each have a function of retaining 1-bit complementary data written from the third circuit.

    Abstract translation: 提供适用于高速操作的小型半导体器件。 半导体器件包括第一电路，用于写入的全局位线对，用于读取的全局位线对和局部位线对。 第一电路包括第二至第五电路。 第二至第五电路通过局部位线对彼此电连接。 第二个电路用作读/写选择开关。 第三电路用作临时存储1位互补数据的工作存储器。 第四电路具有对本地位线对进行预充电的功能。 第五电路包括n（n为2以上的整数）第六电路。 每个第六电路具有保持从第三电路写入的1位互补数据的功能。

    IMAGING DEVICE, MODULE, ELECTRONIC DEVICE, AND METHOD OF OPERATING THE IMAGING DEVICE
    3.
    发明申请
    IMAGING DEVICE, MODULE, ELECTRONIC DEVICE, AND METHOD OF OPERATING THE IMAGING DEVICE 审中-公开
    成像装置，模块，电子装置和操作成像装置的方法

    公开(公告)号：WO2017042658A1

    公开(公告)日：2017-03-16

    申请号：PCT/IB2016/055137

    申请日：2016-08-29

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： OHMARU, Takuro

    IPC: H01L27/146 ,  H01L21/8234 ,  H01L27/00 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/14 ,  H01L29/786 ,  H04N5/355 ,  H04N5/374

    CPC classification number: H04N5/378 ,  H01L27/14612 ,  H01L27/14638 ,  H04N5/35581 ,  H04N5/3575 ,  H04N5/359 ,  H04N5/3698 ,  H04N5/37452

    Abstract: An imaging device whose dynamic range can be wide with a simple structure is provided. In a circuit configuration and an operation method of the imaging device, whether a charge detection portion provided in a pixel is saturated with electrons is determined and an operation mode is changed depending on the determination result. First imaging data is captured first, and is read out in the case where the charge detection portion is not saturated with electrons. In the case where the charge detection portion is saturated with electrons, the saturation of the charge detection portion is eliminated and second imaging data is captured and read out.

    Abstract translation: 提供一种其结构简单的动态范围广的成像装置。 在成像装置的电路配置和操作方法中，确定像素中的电荷检测部分是否饱和电子，并且根据确定结果改变操作模式。 首先捕获第一成像数据，并且在电荷检测部未饱和的情况下读出。 在充电检测部分被电子饱和的情况下，电荷检测部分的饱和度被消除，并且第二成像数据被捕获和读出。

    HOLDING CIRCUIT, DRIVING METHOD OF THE HOLDING CIRCUIT, AND SEMICONDUCTOR DEVICE INCLUDING THE HOLDING CIRCUIT
    4.
    发明申请
    HOLDING CIRCUIT, DRIVING METHOD OF THE HOLDING CIRCUIT, AND SEMICONDUCTOR DEVICE INCLUDING THE HOLDING CIRCUIT 审中-公开
    保持电路的保持电路，驱动方法和包括保持电路的半导体器件

    公开(公告)号：WO2015155633A1

    公开(公告)日：2015-10-15

    申请号：PCT/IB2015/052384

    申请日：2015-04-01

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： OHMARU, Takuro

    IPC: H03K3/037 ,  H01L21/8234 ,  H01L27/088 ,  H03K3/356

    CPC classification number: G11C19/184 ,  G11C11/24 ,  G11C11/405 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H03K3/356008 ,  H03K17/005 ,  H03K19/0016

    Abstract: A holding circuit includes first to third input terminals, an output terminal, first to third switches, a capacitor, and a node. The first to third switches control conduction between the node and the first input terminal, conduction between the node and the output terminal, and conduction between the second input terminal and the output terminal, respectively. First and second terminals of the capacitor are electrically connected to the node and the third input terminal, respectively. The first to third switches are each a transistor comprising an oxide semiconductor layer comprising a semiconductor region. Owing to the structure, a potential change of the node in an electrically floating state can be suppressed; thus, the holding circuit can retain its state for a long time. The holding circuit can be used as a memory circuit for backup of a sequential circuit, for example.

    Abstract translation: 保持电路包括第一至第三输入端子，输出端子，第一至第三开关，电容器和节点。 第一至第三开关控制节点与第一输入端之间的导通，节点与输出端之间的导通，以及第二输入端和输出端之间的导通。 电容器的第一和第二端子分别电连接到节点和第三输入端子。 第一至第三开关分别为包括半导体区域的氧化物半导体层的晶体管。 由于该结构，可以抑制电浮动状态下的节点的潜在变化; 因此，保持电路可以长时间保持其状态。 例如，保持电路可以用作用于备份时序电路的存储电路。

    POWER SOURCE CIRCUIT
    7.
    发明申请
    POWER SOURCE CIRCUIT 审中-公开
    电源电路

    公开(公告)号：WO2011129209A1

    公开(公告)日：2011-10-20

    申请号：PCT/JP2011/058487

    申请日：2011-03-29

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  ITO, Yoshiaki ,  OHMARU, Takuro

    Inventor： ITO, Yoshiaki ,  OHMARU, Takuro

    IPC: H02M3/155 ,  H03K7/08

    CPC classification number: H02M3/157 ,  G05F1/00 ,  G09G3/10

    Abstract: An object is to reduce degradation of circuit operation and to reduce the area of the entire circuit. A power source circuit is provided with a first terminal to which first voltage is input; a second terminal to which second voltage is input; a comparator being connected to the first terminal and the second terminal and comparing the first voltage and the second voltage; a digital circuit averaging, integrating, and digital pulse width modulating a first digital signal output from the comparator; a PWM output driver amplifying a second digital signal output from the digital circuit; and a smoothing circuit smoothing the amplified second digital signal.

    Abstract translation: 目的是减少电路运行的恶化并减少整个电路的面积。 电源电路设置有输入第一电压的第一端子; 输入第二电压的第二端子; 比较器连接到第一端子和第二端子，并且比较第一电压和第二电压; 数字电路对从比较器输出的第一数字信号进行平均，积分和数字脉宽调制; PWM输出驱动器，放大从数字电路输出的第二数字信号; 以及使放大的第二数字信号平滑的平滑电路。

    PWM LIMITER CIRCUIT
    8.
    发明申请
    PWM LIMITER CIRCUIT 审中-公开
    PWM限幅电路

    公开(公告)号：WO2011052357A1

    公开(公告)日：2011-05-05

    申请号：PCT/JP2010/067606

    申请日：2010-09-30

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ,  OHMARU, Takuro ,  ITO, Yoshiaki

    Inventor： OHMARU, Takuro ,  ITO, Yoshiaki

    IPC: H02M3/00 ,  H02M1/08

    CPC classification number: H03K7/08

    Abstract: The duty ratio of a PWM signal is prevented from being zero immediately after the start of PWM control, for example. A PWM limiter circuit has a structure with which a signal output from the PWM limiter circuit can be prevented from being higher than a certain value or lower than a certain value. The PWM limiter circuit includes a comparator circuit, a controller circuit, and a switch circuit. The highest duty ratio reference voltage V refH is input to a first input terminal. The lowest duty ratio reference voltage V refL is input to a second input terminal. Voltage V err output from an error amplifier is input to a third input terminal.

    Abstract translation: 例如，在PWM控制开始之后PWM信号的占空比被防止为零。 PWM限幅电路具有可以防止从PWM限幅电路输出的信号高于某一值或低于某一值的结构。 PWM限幅器电路包括比较器电路，控制器电路和开关电路。 最高占空比参考电压V refH被输入到第一输入端。 最低占空比参考电压V refL被输入到第二输入端。 从误差放大器输出的电压V err被输入到第三输入端。

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