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    REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE
    1.
    发明申请
    REDUCING VERIFICATION CHECKS WHEN PROGRAMMING A MEMORY DEVICE 审中-公开
    编程存储设备时减少验证检查

    公开(公告)号：WO2017099927A1

    公开(公告)日：2017-06-15

    申请号：PCT/US2016/061006

    申请日：2016-11-08

    Applicant: INTEL CORPORATION

    Inventor： KAVALIPURAPU, Kalyan ,  VAHIDIMOWLAVI, Allahyar ,  YU, Erwin

    IPC: G11C16/34

    CPC classification number: G11C16/3459 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/4076 ,  G11C11/5628 ,  G11C16/3445 ,  G11C16/3454 ,  G11C2211/5621

    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.

    Abstract translation: 描述了一种设备的技术。 该设备可以包括具有电路的存储器控​​制器，该电路被配置为启动编程验证序列以验证写入到非易失性存储器（NVM）的数据。 编程验证序列可以具有一个或多个编程验证电平，每个编程验证电平对应于正在验证写入数据的NVM中的存储单元。 存储器控制器可以为成功写入数据的每个编程验证电平检测存储单元的近似百分比。 当成功写入数据的存储器单元的大致百分比小于定义的阈值时，存储器控制器可以确定跳过在一个或多个编程验证电平中的随后的编程脉冲验证检查。

    ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE DETECTION
    3.
    发明申请
    ON DEMAND KNOCKOUT OF COARSE SENSING BASED ON DYNAMIC SOURCE BOUNCE DETECTION 审中-公开
    基于动态源检测的干扰检测需求分析

    公开(公告)号：WO2017048414A1

    公开(公告)日：2017-03-23

    申请号：PCT/US2016/046173

    申请日：2016-08-09

    Applicant: INTEL CORPORATION ,  KAVALIPURAPU, Kalyan C. ,  PARK, Jae-Kwan ,  YU, Erwin E. ,  PICCARDI, Michele

    Inventor： KAVALIPURAPU, Kalyan C. ,  PARK, Jae-Kwan ,  YU, Erwin E. ,  PICCARDI, Michele

    IPC: G11C16/34 ,  G11C16/04 ,  G06F11/10

    CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3454

    Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.

    Abstract translation: 系统，装置和方法可以提供用于确定与一个或多个存储器单元相关联的源极线上的反弹电压的大小，并且如果反弹电压的大小超过阈值，则进行粗略级程序验证， 一个或多个存储器单元的级别程序验证。 此外，如果反弹电压的大小不超过阈值，则只能执行一个或多个存储器单元的精细级程序验证。 在一个示例中，如果反弹电压的幅度不超过阈值，则旁路粗略级程序验证。

    BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS
    4.
    发明申请
    BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS 审中-公开
    位线和比较电压调制非感觉非易失性存储元件

    公开(公告)号：WO2015053919A1

    公开(公告)日：2015-04-16

    申请号：PCT/US2014/056403

    申请日：2014-09-18

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： DUNGA, Mohan V. ,  HIGASHITANI, Masaaki

    IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C5/14 ,  G11C16/24 ,  G11C7/12

    CPC classification number: G11C16/3454 ,  G11C7/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

    Abstract: In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

    Abstract translation: 在一块非易失性存储器中，位线电流随着位线电压而增加。 对于电流感测存储器系统，感测操作期间的平均位线电流仅需要超过特定的阈值量以产生正确的结果。 对于在块中被编程的第一字线，与其连接的存储器单元在验证操作期间看到相对较低的位线电阻。 在所公开的技术中，针对具有较低验证位线电压的这些第一经编程字线执行验证操作，以便减少过量位线电流且节省功率。 在读操作期间，该方案可以使连接到较低字线的存储单元的阈值电压看起来较低。 为了弥补这种影响，公开了各种方案。

    DATA STORAGE SYSTEM WITH DYNAMIC READ THRESHOLD MECHANISM AND METHOD OF OPERATION THEREOF
    5.
    发明申请
    DATA STORAGE SYSTEM WITH DYNAMIC READ THRESHOLD MECHANISM AND METHOD OF OPERATION THEREOF 审中-公开
    具有动态读取机械的数据存储系统及其操作方法

    公开(公告)号：WO2015017719A1

    公开(公告)日：2015-02-05

    申请号：PCT/US2014/049282

    申请日：2014-07-31

    Applicant: SMART STORAGE SYSTEMS, INC.

    Inventor： FITZPATRICK, James ,  DANCHO, Mark ,  HIGGINS, James, M. ,  ELLIS, Robert, W.

    IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/06

    CPC classification number: G06F12/00 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/349

    Abstract: A system and method of operation of a data storage system includes: a memory die for determining a middle read threshold (312); a control unit, coupled to the memory die, for calculating a lower read threshold (310) and an upper read threshold (314) based on the middle read threshold and a memory element age; and a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

    Abstract translation: 数据存储系统的操作系统和方法包括：用于确定中间读取阈值（312）的存储器管芯; 耦合到所述存储器管芯的控制单元，用于基于所述中间读取阈值和存储器元件寿命来计算下部读取阈值（310）和上部读取阈值（314）; 以及耦合到存储器管芯的存储器接口，用于使用较低读取阈值，中间读取阈值或上部读取阈值读取存储器管芯的存储器页面，以补偿电荷变化。

    DETECTING PROGRAMMED WORD LINES BASED ON NAND STRING CURRENT
    6.
    发明申请
    DETECTING PROGRAMMED WORD LINES BASED ON NAND STRING CURRENT 审中-公开
    基于NAND STRING电流检测编程的字线

    公开(公告)号：WO2015002901A1

    公开(公告)日：2015-01-08

    申请号：PCT/US2014/044953

    申请日：2014-06-30

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： MUI, Man, L. ,  DONG, Yingda ,  AVILA, Chirs

    IPC: G11C11/56 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C11/5635 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/26 ,  G11C16/344 ,  G11C16/3454

    Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.

    Abstract translation: 通过在所有存储单元处于导通状态时测量块中的参考组合电流（Iref）来确定NAND串块中的编程字线的数量（Nwl）。 随后，为了确定字线是否是编程字线，块中的附加组合电流（Iadd）是用施加到所选字线的分界电压来测量的。 如果Idd小于Iref至少有余量，则所选字线被确定为编程字线。 当数字相对较小时，通过使擦除验证测试相对难于通过，当数量相对较大时，Nwl可用于调整擦除操作的擦除验证测试。 或者，Nwl可用于标识块中的下一个字线进行编程。

    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    9.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING 审中-公开
    用于数据传感的方法，设备和系统

    公开(公告)号：WO2012125542A1

    公开(公告)日：2012-09-20

    申请号：PCT/US2012/028745

    申请日：2012-03-12

    Applicant: MICRON TECHNOLOGY, INC. ,  HELM, Mark A. ,  CHANDRASEKHAR, Uday

    Inventor： HELM, Mark A. ,  CHANDRASEKHAR, Uday

    IPC: G11C7/22 ,  G11C7/10 ,  G11C29/42

    CPC classification number: G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

    Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

    Abstract translation: 本公开包括用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出与多个连续感测操作中的一个相对应的硬数据。

    NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY
    10.
    发明申请
    NATURAL THRESHOLD VOLTAGE DISTRIBUTION COMPACTION IN NON-VOLATILE MEMORY 审中-公开
    非易失性存储器中的自然阈值电压分配压缩

    公开(公告)号：WO2012018765A1

    公开(公告)日：2012-02-09

    申请号：PCT/US2011/046197

    申请日：2011-08-02

    Applicant: SANDISK TECHNOLOGIES, INC. ,  DUTTA, Deepanshu ,  LUTZE, Jeffrey, W.

    Inventor： DUTTA, Deepanshu ,  LUTZE, Jeffrey, W.

    IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

    Abstract: In a non-volatile memory system, a programming speed-based slow down measure such as a raised bit line is applied to the faster-programming storage elements. A multi-phase programming operation which uses a back- and-forth word line order is performed in which programming speed data is stored in latches in one programming phase and read from the latches for use in a subsequent programming phase of a given word line. The faster and slower- programming storage elements can be distinguished by detecting when a number of storage elements reach a specified verify level, counting an additional number of program pulses which is set based on a natural threshold voltage distribution of the storage elements, and subsequently performing a read operation that separates the faster and slower programming storage elements. A drain-side select gate voltage can be adjusted in different programming phases to accommodate different bit line bias levels.

    Abstract translation: 在非易失性存储器系统中，基于速度的编程速度减慢测量例如升高的位线被应用于更快编程的存储元件。 执行使用来回字线顺序的多相编程操作，其中编程速度数据被存储在一个编程阶段的锁存器中，并且从锁存器读取以用于给定字线的后续编程阶段。 可以通过检测多个存储元件何时达到指定的验证电平，计数基于存储元件的自然阈值电压分布而设置的附加数量的编程脉冲，然后执行 一种分离更快和慢速编程存储元件的读取操作。 可以在不同的编程阶段调整漏极侧选择栅极电压，以适应不同的位线偏置电平。

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