公开(公告)号：WO2021259477A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067772

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L2224/03845 ,  H01L2224/04105 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06593 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50

Abstract: A method of stacking semiconductor components, to obtain a semiconductor wafer assembly, and for forming a semiconductor die assembly therefrom, is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively; providing at least a third and a fourth die, to be stacked on the first and the second die, respectively; placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively; applying insulating material on the carrier wafer outside of the third and the fourth dies; and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

公开(公告)号：WO2022126016A2

公开(公告)日：2022-06-16

申请号：PCT/US2021/063094

申请日：2021-12-13

Applicant: QORVO US, INC.

Inventor： COSTA, Julio C. ,  MAXIM, George ,  SCOTT, Baker

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2225/1041 ,  H01L2225/1047 ,  H01L2225/1088 ,  H01L24/10 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2924/10329

Abstract: The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.

公开(公告)号：WO2022187776A2

公开(公告)日：2022-09-09

申请号：PCT/US2022/070496

申请日：2022-02-03

Applicant: QUALCOMM INCORPORATED

Inventor： ZHOU, Rong ,  ADERHOLDT, William M.

IPC: H01L23/498 ,  H01L21/60 ,  H01L25/065 ,  H01L23/538 ,  H01L2224/0401 ,  H01L2224/06152 ,  H01L2224/06156 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/14152 ,  H01L2224/14156 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/96 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/20 ,  H01L25/0655 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/37001

Abstract: Aii integrated circuit (IC) package including ICs (204) with multi- row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters (202(1), 202(2)), that each include a plurality of die interconnect rows (213,214) and two columns (200A,200B), reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects (206). A die interconnect column cluster pitch (Pcc2) is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch (PDir2) between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration.

公开(公告)号：WO2021259607A1

公开(公告)日：2021-12-30

申请号：PCT/EP2021/064819

申请日：2021-06-02

Applicant: NANOWIRED GMBH

Inventor： QUEDNAU, Sebastian ,  ROUSTAIE, Farough ,  DASSINGER, Florian ,  BIRLEM, Olav

IPC: H01L27/146 ,  H01L23/00 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13078 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81897 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469

Abstract: Verfahren zum Verbinden eines ersten Waferelements (1) mit einem zweiten Waferelement (2), wobei das erste Waferelement (1) eine Mehrzahl von ersten Bauteilbereichen (3) mit einer jeweiligen elektronischen Struktur (5) und einer jeweiligen Kontaktfläche (6) aufweist, wobei das zweite Waferelement (2) eine Mehrzahl von zweiten Bauteilbereichen (4) mit einer jeweiligen elektronischen Struktur (5) und einer jeweiligen Kontaktfläche (6) aufweist, wobei die Waferelemente (1,2) dadurch miteinander verbunden werden, dass die Kontaktflächen (6) der beiden Waferelemente (1,2) paarweise über eine Vielzahl von Nanodrähten (7) miteinander verbunden werden.

公开(公告)号：WO2021253573A1

公开(公告)日：2021-12-23

申请号：PCT/CN2020/104571

申请日：2020-07-24

Applicant: 珠海越亚半导体股份有限公司

Inventor： 陈先明 ,  谢炳森 ,  黄本霞 ,  冯磊

IPC: H01L23/552 ,  H01L21/4853 ,  H01L21/486 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/15153

Abstract: 本申请公开了一种散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板，该散热兼电磁屏蔽嵌埋封装结构包括：介质层，包括上表面和下表面，介质层内部设置有至少一个空腔单元；绝缘层，设置于空腔单元中，空腔单元被绝缘层部分填充；电子元件，一端嵌埋于绝缘层中，另一端外露于空腔单元中，电子元件包括端子；通孔，贯穿于介质层的上表面和下表面，并与端子连通；金属层，覆盖在介质层的六个表面和通孔内，分别用于形成屏蔽层和线路层，屏蔽层覆盖电子元件外露一端，屏蔽层与线路层通过介质层阻隔。本申请的散热兼电磁屏蔽嵌埋封装结构及其制作方法和基板能够同时实现较好的电磁辐射屏蔽和散热功能。