Invention Grant
- Patent Title: High performance interconnect
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Application No.: US18347236Application Date: 2023-07-05
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Publication No.: US12189550B2Publication Date: 2025-01-07
- Inventor: Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F13/22
- IPC: G06F13/22 ; G06F1/3287 ; G06F8/71 ; G06F8/77 ; G06F9/30 ; G06F9/445 ; G06F9/46 ; G06F11/10 ; G06F12/0806 ; G06F12/0808 ; G06F12/0813 ; G06F12/0815 ; G06F12/0831 ; G06F13/40 ; G06F13/42 ; H04L9/06 ; H04L49/15 ; G06F8/73 ; H04L12/46 ; H04L45/74

Abstract:
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
Public/Granted literature
- US20240012772A1 HIGH PERFORMANCE INTERCONNECT Public/Granted day:2024-01-11
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