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    Apparatus, system and method to detect and improve an input clock performance of a memory device
    3.
    发明授权
    Apparatus, system and method to detect and improve an input clock performance of a memory device 有权

    公开(公告)号：US12217787B2

    公开(公告)日：2025-02-04

    申请号：US17349854

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Arvind A. Kumar ,  James Alexander McCall ,  Bill H. Nale ,  John R. Goles ,  Dean-Dexter R. Eugenio

    IPC: G06F1/12 ,  G06F1/08 ,  G06F13/16 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.

    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing
    8.
    发明授权
    Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing 有权

    公开(公告)号：US09817054B2

    公开(公告)日：2017-11-14

    申请号：US13729756

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Thanunathan Rangarajan ,  Shreesh Chhabbi ,  Arvind A. Kumar ,  Venkatraman Iyer

    IPC: G01R31/04 ,  G01R31/30

    CPC classification number: G01R31/04 ,  G01R31/30

    Abstract: Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.

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