公开(公告)号：EP2831693A4

公开(公告)日：2015-10-21

申请号：EP12873212

申请日：2012-03-30

申请人： INTEL CORP

发明人： WEISSMANN ELIEZER ,  VAITHIANATHAN KARTHIKEYAN KARTHIK ,  ZACH YOAV ,  GINZBURG BORIS ,  RONEN RONNY

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/38 ,  G06F12/10 ,  G06F13/14

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP2831693A1

公开(公告)日：2015-02-04

申请号：EP12873212.0

申请日：2012-03-30

申请人： Intel Corporation

发明人： WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  ZACH, Yoav ,  GINZBURG, Boris ,  RONEN, Ronny

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F12/10 ,  G06F13/14

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

摘要翻译： 的装置和方法被描述用于耦合前端促进剂组分的芯（E. G，：诸如图形加速器）。 例如，为了装置进行说明，包括：加速器，包括一个或多个执行单元（EU）来执行指定的一组指令; 和前端芯，包括翻译旁视缓冲器（TLB）通信地耦合到所述加速器和所述加速器提供存储器访问服务，则存储器访问的服务，包括执行TLB查找操作以映射虚拟地址到物理地址代表在响应所述加速器和 在加速器需要访问系统内存。

公开(公告)号：EP2581833A4

公开(公告)日：2014-12-31

申请号：EP10852885

申请日：2010-06-10

申请人： FUJITSU LTD

发明人： KURIHARA KOJI ,  YAMASHITA KOICHIRO ,  YAMAUCHI HIROMASA

IPC分类号： G06F12/08 ,  G06F9/50 ,  G06F12/12

CPC分类号： G06F12/0842 ,  G06F9/5088 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/126 ,  G06F2209/507 ,  G06F2212/1016 ,  G06F2212/452

公开(公告)号：EP2798471A1

公开(公告)日：2014-11-05

申请号：EP11879070.8

申请日：2011-12-30

申请人： Intel Corporation

发明人： MCNAIRY, Cameron B.

IPC分类号： G06F9/06 ,  G06F9/30 ,  G06F13/14

CPC分类号： G06F15/76 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/3824 ,  G06F11/1064 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0875 ,  G06F2015/765 ,  G06F2212/452

摘要： A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of the structure but are able to access one or more other portions of the structure. Non-architecturally visible data in the portion of the structure is modified, while the portion of the structure is in the sequestered state. The state of the portion of the structure is then changed from the sequestered state to a non-sequestered state, after the non-architecturally visible data in the portion of the structure has been modified. Other methods, apparatus, systems, and instructions are also disclosed.

摘要翻译： 可以响应于一个或多个结构访问指令执行的方面的方法包括将处理器的结构的一部分的状态改变为隔离状态。 在隔离状态下，处理器的组件不能访问结构的部分，但是能够访问结构的一个或多个其他部分。 在结构部分中的非结构可视数据被修改，而结构的部分处于隔离状态。 在结构部分中的非结构化可见数据已被修改之后，结构部分的状态然后从隔离状态改变为非隔离状态。 还公开了其它方法，装置，系统和指令。

公开(公告)号：EP2798470A1

公开(公告)日：2014-11-05

申请号：EP11878987.4

申请日：2011-12-29

申请人： Intel Corporation

发明人： STAVROU, Kyriakos A. ,  GIBERT CODINA, Enric ,  CODINA, Josep M. ,  GOMEZ REQUENA, Crispin ,  GONZALEZ, Antonio ,  HYUSEINOVA, Mirem ,  KOTSELIDIS, Christos E. ,  LATORRE, Fernando ,  LOPEZ, Pedro ,  LUPON, Marc ,  MADRILES, Carlos ,  MAGKLIS, Grigorios ,  MARCUELLO, Pedro ,  MARTINEZ VICENTE, Alejandro ,  MARTINEZ, Raul ,  ORTEGA, Daniel ,  PAVLOU, Demos ,  TOURNAVITIS, Georgios ,  XEKALAKIS, Polychronis

IPC分类号： G06F9/06 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

公开(公告)号：EP2689326A4

公开(公告)日：2014-10-22

申请号：EP12763717

申请日：2012-03-23

申请人： SOFT MACHINES INC

发明人： ABDALLAH MOHAMMAD

IPC分类号： G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F15/76

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3889 ,  G06F9/5027 ,  G06F12/0875 ,  G06F2209/507 ,  G06F2212/452 ,  Y02D10/22

摘要： A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

公开(公告)号：EP2668565A4

公开(公告)日：2014-09-03

申请号：EP12739955

申请日：2012-01-25

申请人： SOFT MACHINES INC

发明人： ABDALLAH MOHAMMAD

IPC分类号： G06F9/06 ,  G06F9/30 ,  G06F9/305 ,  G06F9/45 ,  G06F12/08

CPC分类号： G06F12/0875 ,  G06F8/52 ,  G06F9/30058 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3808 ,  G06F2212/151 ,  G06F2212/452

摘要： A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

公开(公告)号：EP2433227A1

公开(公告)日：2012-03-28

申请号：EP10731653.1

申请日：2010-06-25

申请人： Simplivity Corporation

发明人： BOWDEN, Paul ,  BEAVERSON, Arthur, J.

IPC分类号： G06F17/30

CPC分类号： G06F12/1054 ,  G06F12/0246 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1408 ,  G06F17/30097 ,  G06F17/30949 ,  G06F17/30952 ,  G06F2212/2542 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/6032 ,  G06F2212/7211

摘要： Method and apparatus for constructing an index that scales to a large number of records and provides a high transaction rate. New data structures and methods are provided to ensure that an indexing algorithm performs in a way that is natural (efficient) to the algorithm, while a non-uniform access memory device sees IO (input/output) traffic that is efficient for the memory device. One data structure, a translation table, is created that maps logical buckets as viewed by the indexing algorithm to physical buckets on the memory device. This mapping is such that write performance to non¬ uniform access SSD and flash devices is enhanced. Another data structure, an associative cache is used to collect buckets and write them out sequentially to the memory device as large sequential writes. Methods are used to populate the cache with buckets (of records) that are required by the indexing algorithm. Additional buckets may be read from the memory device to cache during a demand read, or by a scavenging process, to facilitate the generation of free erase blocks.

摘要翻译： 用于构建可扩展到大量记录并提供高事务率的索引的方法和设备。 提供新的数据结构和方法以确保索引算法以对算法而言自然（高效）的方式执行，而非均匀访问存储器设备看到对存储器设备有效的IO（输入/输出）流量 。 创建一个数据结构，一个转换表，将由索引算法查看的逻辑存储区映射到存储设备上的物理存储区。 这种映射使得写入到非统一访问SSD和闪存设备的性能得到增强。 另一种数据结构，即关联缓存用于收集存储桶，并将其按顺序写入存储设备作为大量顺序写入。 方法用于使用索引算法所需的存储桶（记录）填充高速缓存。 可以在需求读取期间或通过清除过程从存储器设备中读取额外的存储桶以缓存以便于产生自由擦除块。

公开(公告)号：EP1994534A1

公开(公告)日：2008-11-26

申请号：EP07752961.8

申请日：2007-03-13

申请人： Micron Technology, Inc.

发明人： DE SANTIS, Luca ,  PILOLLI, Luigi

IPC分类号： G11C16/06 ,  G11C7/10 ,  G11C17/10

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/1668 ,  G06F2212/2022 ,  G06F2212/452 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/16 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/06 ,  G11C16/10 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

摘要： Apparatus including a memory array further include an analog voltage generation circuit, an analog controller, a data cache, a data cache controller, and a master controller. The master controller is configured to generate an indication in response to an interpreted command. The analog controller is configured to determine, in response to the indication, what analog voltages should be generated by the analog voltage generation circuit for the apparatus to perform the interpreted command. The data cache controller is configured to determine, in response to the indication, whether the data cache should be configured to accept data from the memory array or to provide data to the memory array for the apparatus to perform the interpreted command.

公开(公告)号：EP3384400A1

公开(公告)日：2018-10-10

申请号：EP16871210.7

申请日：2016-09-27

申请人： Intel Corporation

发明人： LINSKY, Leo A.

IPC分类号： G06F15/80 ,  G06F12/0811

CPC分类号： G06F9/30029 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3897 ,  G06F12/0811 ,  G06F12/0875 ,  G06F15/7807 ,  G06F15/80 ,  G06F2212/452 ,  Y02D10/12 ,  Y02D10/13

摘要： In one embodiment, a processor includes: a first core to execute instructions; and a programmable fabric having a hierarchical arrangement including a first layer of programmable fabric and a second layer of programmable fabric. The programmable fabric may include a fabric interface controller to: receive a first programmable fabric control instruction from the first core; and responsive thereto, cause a first programmable fabric unit of the first layer of programmable fabric to execute an operation on first input data. Other embodiments are described and claimed.