公开(公告)号：EP0039411B1

公开(公告)日：1985-01-30

申请号：EP81102499.1

申请日：1981-04-02

申请人： International Business Machines Corporation

发明人： Horng, Cheng Tzong ,  Konian, Richard Robert ,  Schwenker, Robert Otto ,  Wieder, Armin Wilhelm

IPC分类号： H01L27/08 ,  H01L21/82

CPC分类号： H01L29/66272 ,  H01L21/76202 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/7325 ,  H01L29/735

公开(公告)号：EP0118102A2

公开(公告)日：1984-09-12

申请号：EP84102143.9

申请日：1984-02-29

申请人： HITACHI, LTD.

发明人： Nakazato, Kazuo ,  Nakamura, Tohru ,  Miyazaki, Takao ,  Natsuaki, Nobuyoshi ,  Ogirima, Masahiko ,  Nagata, Minoru

IPC分类号： H01L21/285 ,  H01L29/72 ,  H01L27/06

CPC分类号： H01L29/66272 ,  H01L21/8222 ,  H01L29/72 ,  H01L29/7325

摘要： The invention deals with a semiconductor device which comprises a semiconductor substrate (11) of a first conductivity type, a semiconductor region (14, 15) formed on said substrate, and a first insulation film (120, 77) provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer (79, 121) formed in the periphery of said semiconductor region (14, 15) thereby to reduce the parasitic capacitance, and wherein said insulation film (79, 121) is stretched and arranged on the lower side of said semiconductor region.

公开(公告)号：EP0036499B1

公开(公告)日：1984-08-15

申请号：EP81101364.8

申请日：1981-02-25

申请人： International Business Machines Corporation

发明人： Ho, Allen Pang-I ,  Horng, Cheng Tzong

IPC分类号： H01L21/00 ,  H01L21/285 ,  H01L21/60 ,  H01L21/76 ,  H01L29/72

CPC分类号： H01L29/7325 ,  H01L21/0337 ,  H01L29/66272

公开(公告)号：EP0106254A2

公开(公告)日：1984-04-25

申请号：EP83109863.7

申请日：1983-10-03

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Mader, Hermann, Dr.

IPC分类号： H01L29/10 ,  H01L29/72

CPC分类号： H01L29/7325 ,  H01L29/7606

摘要： Die Erfindung betrifft einen Transistor mit einstellbarer Energiebarriere und mit ohmschen Kontakten, der eine n + pn- oder p + np-Dreischichtstruktur (1, 2, 3) mit so dünn ausgebildeter mittlerer Schicht (2) (Basis) aufweist, daß bereits ohne äußbere, an die Elektroden angelegte elektrische Spannung bei der gegebenen Dotierung dieser Schicht (2) ihr gesamter Bereich an freien Ladungsträgern verarmt ist. Für die Dotierungsdichten N von Emitter (E)-, Basis (B)-und Kollektorzone (C) gilt: N E > N B > N c . Die Steuerung des Kollektorstromes erfolgt über die Änderung einer Energiebarriere für Majoritätsträger mit einer angelegten Basis-Emitter-Spannung im Gegensatz zum Bipolartransistor, bei dem die Kollektorstromsteuerung durch Änderung der Minoritätsträgerdichte in der Basis mit einer angelegten Basis-Emitter-Spannung erfolgt. Der Anwendungsbereich erstreckt sich auf diskrete bipolare Halbleiterbauelemente und auf integrierte Schaltungen; Verwendung als Verstärker, Schalter, Mischer, Oszillator und Temperatursensor.

摘要翻译： 具有可调能量势垒并具有欧姆接触的晶体管，具有具有中心层（2）基极的n + pn或p + np三层结构（1,2,3），其具有如此薄，使得即使 没有施加到电极的电压，该层（2）的整个区域以其给定的掺杂水平耗尽自由电荷载流子。 发射极（E），基极（B）和集电极（C）区域的掺杂密度N满足NE> NB> NC要求。 通过用施加的基极 - 发射极电压改变多数载流子的能量势垒来控制集电极电流，与双极晶体管相反，双极晶体管通过施加的基极 - 发射极电压来改变基极中的少数载流子密度来控制集电极电流 。 应用领域包括分立双极半导体器件和集成电路; 用作放大器，开关，混频器，振荡器和温度传感器。

公开(公告)号：EP0035126A3

公开(公告)日：1982-09-01

申请号：EP81100812

申请日：1981-02-05

申请人： International Business Machines Corporation

发明人： Horng, Cheng Tzong ,  Schwenker, Robert Otto ,  Tsang, Paul Ja-Min

IPC分类号： H01L21/76 ,  H01L21/60 ,  H01L21/00 ,  H01L29/08 ,  H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/131 ,  Y10S438/951

摘要： Disclosed is a self-aligned process for providing an improved bipolar transistor structure. The process includes the chemically etching of an intermediate insulating layer (10) to undercut another top layer (11) of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug (14) is formed to block the emitter region (12) from the heavy P+ ion dose implant of the extrinsic base (19).

公开(公告)号：EP0035126A2

公开(公告)日：1981-09-09

申请号：EP81100812.7

申请日：1981-02-05

申请人： International Business Machines Corporation

发明人： Horng, Cheng Tzong ,  Schwenker, Robert Otto ,  Tsang, Paul Ja-Min

IPC分类号： H01L21/76 ,  H01L21/60 ,  H01L21/00 ,  H01L29/08 ,  H01L29/72

CPC分类号： H01L21/76897 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76229 ,  H01L29/0804 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/131 ,  Y10S438/951

摘要： Disclosed is a self-aligned process for providing an improved bipolar transistor structure.
The process includes the chemically etching of an intermediate insulating layer (10) to undercut another top layer (11) of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug (14) is formed to block the emitter region (12) from the heavy P+ ion dose implant of the extrinsic base (19).

公开(公告)号：EP1863096B1

公开(公告)日：2017-07-19

申请号：EP06011118.4

申请日：2006-05-30

申请人： Nissan Motor Company Limited

发明人： Shimoida, Yoshio ,  Hoshi, Masakatsu ,  Hayashi, Tetsuya ,  Tanaka, Hideaki

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L21/04 ,  H01L29/808 ,  H01L29/812 ,  H01L29/732 ,  H01L29/24 ,  H01L29/20 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7325 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8122

摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate (1,2); and a switching mechanism (6,7,10) which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions (4) are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.

摘要翻译： 本发明的半导体器件包括第一导电型半导体基础衬底（1,2）; 以及切换机构（6,7,10），其形成在半导体基础基板的第一主表面上并接通/断开电流。 在半导体基础衬底中，在半导体衬底内以间隔开的间隔形成多个柱状异质半导体区域（4），并且异质半导体区域由具有与半导体衬底不同的带隙的半导体材料制成， 在第一主表面和与第一主表面相对的第二主表面之间。

公开(公告)号：EP2345063A2

公开(公告)日：2011-07-20

申请号：EP09818093.8

申请日：2009-09-29

申请人： Northrop Grumman Systems Corporation

发明人： VELIADIS, John, Victor, D. ,  McNUTT, Ty, R.

IPC分类号： H01L21/265 ,  H01L29/70 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7325 ,  H01L29/7395 ,  H01L29/7722 ,  H01L29/7811 ,  H01L29/8083 ,  H01L29/8613 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.

公开(公告)号：EP1883102A3

公开(公告)日：2009-04-22

申请号：EP06255833.3

申请日：2006-11-15

申请人： Central Research Institute of Electric Power Industry

发明人： Tsuchida, Hidekazu Materials Science Research Lab. ,  Storasta, Liutauras Materials Science Res. Lab.

IPC分类号： H01L21/04 ,  H01L21/265 ,  H01L29/24 ,  H01L21/322 ,  H01L29/732 ,  H01L29/74 ,  H01L29/861 ,  H01L29/739

CPC分类号： H01L21/0445 ,  C30B29/36 ,  C30B31/22 ,  H01L21/322 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/7325 ,  H01L29/7395

摘要： It is an object to provide a method for improving the quality of an SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and an SiC semiconductor device fabricated by the method.
A method for improving the quality of an SiC layer by eliminating or reducing some carrier trapping centers comprising the steps of:
(a) carrying out ion implantation of carbon atoms (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and
(b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. A semiconductor device according to the invention is fabricated by the method.

公开(公告)号：EP0395358B1

公开(公告)日：2001-03-14

申请号：EP90304401.4

申请日：1990-04-24

申请人： Matsushita Electronics Corporation

发明人： Sawada, Shigeki

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/331

CPC分类号： H01L21/76897 ,  H01L21/2257 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/123 ,  Y10S148/124