公开(公告)号：EP3314666A1

公开(公告)日：2018-05-02

申请号：EP15896570.7

申请日：2015-06-26

申请人： INTEL Corporation

发明人： DEWEY, Gilbert ,  METZ, Matthew V. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  RACHMADY, Willy ,  MOHAPATRA, Chandra S. ,  KAVALIEROS, Jack T. ,  GLASS, Glenn A.

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/8258 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：EP3314663A1

公开(公告)日：2018-05-02

申请号：EP15896564.0

申请日：2015-06-26

申请人： INTEL Corporation

发明人： RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  RAHHAL-ORABI, Nadia M. ,  GARDNER, Sanaz K.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78609 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

摘要： Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

公开(公告)号：EP3314641A1

公开(公告)日：2018-05-02

申请号：EP15896571.5

申请日：2015-06-26

申请人： Intel Corporation

发明人： MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GLASS, Glenn A. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  GHANI, Tahir ,  METZ, Matthew V.

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66522 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

摘要： A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

公开(公告)号：EP3238265A1

公开(公告)日：2017-11-01

申请号：EP14909228.0

申请日：2014-12-23

申请人： Intel Corporation

发明人： GARDNER, Sanaz K. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia ,  ZELICK, Nancy M. ,  FRENCH, Marc C. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

摘要： An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，包括：彼此相邻并且各自包括沟道层和亚鳍层的第一和第二鳍片，沟道层具有与亚鳍层的上表面直接接触的底表面; 其中（a）底面大体上彼此共面且大致平坦; （b）上表面通常彼此共面并且大致平坦; 和（c）沟道层包括上部III-V族材料，亚层包括不同于上部III-V族材料的下部III-V族材料。 这里描述了其他实施例。

公开(公告)号：EP3238263A1

公开(公告)日：2017-11-01

申请号：EP14909206.6

申请日：2014-12-22

申请人： INTEL Corporation

发明人： RAHHAL-ORABI, Nadia M. ,  GHANI, Tahir ,  RACHMADY, Willy ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  DEWEY, Gilbert ,  MURTHY, Anand S. ,  MOHAPATRA, Chandra S.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785

摘要： Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fm.

摘要翻译： 公开了优化用于性能和栅极填充的栅极轮廓的系统和方法。 具有优化的栅极轮廓的半导体器件包括半导体衬底和在半导体衬底上方延伸的鳍。 一对源极和漏极区域设置在沟道区域的相对侧上。 栅极叠层设置在沟道区上方，其中栅极叠层包括通过锥形部分与底部分离的顶部。 锥形部分的顶部和至少一部分设置在翅片上方。

公开(公告)号：EP3195366A1

公开(公告)日：2017-07-26

申请号：EP14901828.5

申请日：2014-09-19

申请人： Intel Corporation

发明人： GLASS, Glenn A. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  METZ, Matthew V. ,  KAVALIEROS, Jack T.

IPC分类号： H01L29/78 ,  H01L21/336

摘要： Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

摘要翻译： 具有砷化铟镓活性沟道的晶体管器件及其制造工艺，当制造鳍状活性沟道（例如在三栅极或全栅（GAA）器件中使用的那些）时，该晶体管器件能够改进载流子迁移率。 在一个实施例中，砷化铟镓材料可以沉积在窄沟槽中，这可以产生具有富铟表面和富镓中心部分的鳍。 这些富含铟的表面将邻接晶体管的栅极氧化物并且可以导致相对于传统的均匀组成铟镓砷活性通道的高电子迁移率和改进的开关速度。

公开(公告)号：EP3195366B1

公开(公告)日：2020-10-21

申请号：EP14901828.5

申请日：2014-09-19

申请人： Intel Corporation

发明人： GLASS, Glenn A. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  METZ, Matthew V. ,  KAVALIEROS, Jack T.

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/04 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/762

公开(公告)号：EP3472867A1

公开(公告)日：2019-04-24

申请号：EP16905666.0

申请日：2016-06-17

申请人： INTEL Corporation

发明人： MA, Sean T. ,  METZ, Matthew V. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L29/423

公开(公告)号：EP3394883A1

公开(公告)日：2018-10-31

申请号：EP15911633.4

申请日：2015-12-22

申请人： Intel Corporation

发明人： RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  KAVALIEROS, Jack T. ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC分类号： H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0886

摘要： Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.

公开(公告)号：EP3238266A1

公开(公告)日：2017-11-01

申请号：EP14909240.5

申请日：2014-12-23

申请人： INTEL Corporation

发明人： KENNEL, Harold W. ,  METZ, Matthew V. ,  RACHMADY, Willy ,  DEWEY, Gilbert ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  KAVALIEROS, Jack T. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/785 ,  H01L29/78681

摘要： Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

摘要翻译： 描述了包括包括第一III-V半导体合金的子鳍和包括第二III-V半导体合金的沟道的半导体器件。 在一些实施例中，半导体器件包括衬底，该衬底包括由至少两个沟槽侧壁限定的沟槽，其中第一III-V半导体合金沉积在沟槽内的衬底上，并且第二III-V半导体合金外延生长在第一 III-V半导体合金。 在一些实施例中，第一III-V半导体合金与第二III-V半导体合金之间的导带偏移大于或等于约0.3电子伏特。 还描述了制造这种半导体器件的方法和包括这种半导体器件的计算设备。