HIGH DENSITY SRAM ARRAY DESIGN WITH WORD LINE LANDING PADS EXTENDING OVER THE CELL BOUNDARY IN THE ROW DIRECTION
    11.
    发明公开
    HIGH DENSITY SRAM ARRAY DESIGN WITH WORD LINE LANDING PADS EXTENDING OVER THE CELL BOUNDARY IN THE ROW DIRECTION 审中-公开
    KONSTRUKTION EINER HOCHDICHTEN SRAM-ARRAY MIT WORTZEILENLANDEPADS,DIEÜBERDIE ZELLENBEGRENZUNG在REIHENRICHTUNG HINAUSGEHEN

    公开(公告)号:EP3117462A1

    公开(公告)日:2017-01-18

    申请号:EP15715628.2

    申请日:2015-03-30

    IPC分类号: H01L27/11 H01L27/02

    CPC分类号: H01L27/1104 H01L27/0207

    摘要: A static random access memory (SRAM) cell (340) includes a first conductive layer (M1) including a wordline landing pad (320) extending into a neighboring memory cell (360) in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline (WL1) coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via (Via0) coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer and a second via (Via1) coupling the wordline landing pad and the wordline of the second conductive layer.

    摘要翻译: 静态随机存取存储器(SRAM)单元包括第一导电层,其包括延伸到存储器阵列的相邻行中的相邻存储器单元的字线着陆焊盘。 第一导电层中的字线着陆焊盘与相邻存储器单元的所有栅极触点电隔离。 SRAM单元还包括第二导电层,其包括耦合到第一导电层中的字线着陆焊盘的字线。 SRAM单元还包括第一通孔,其将SRAM单元中的通过晶体管栅极的栅极接触耦合到第一导电层中的字线着陆焊盘。 SRAM单元还包括连接字线着陆焊盘和第二导电层的字线的第二通孔。

    METHOD AND APPARATUS OF STRESSED FIN NMOS FINFET
    17.
    发明公开
    METHOD AND APPARATUS OF STRESSED FIN NMOS FINFET 审中-公开
    VERFAHREN UND VORRICHTUNGFÜRNMOS-FINFET MIT BELASTETEN RIPPEN

    公开(公告)号:EP3111481A1

    公开(公告)日:2017-01-04

    申请号:EP15710619.6

    申请日:2015-02-17

    IPC分类号: H01L29/78 H01L29/36

    摘要: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

    摘要翻译: 半导体鳍片在基板上,并且在与基板平行的纵向方向上延伸。 翅片在垂直方向上突出到底板上方翅片高度的翅片顶部。 嵌入式翅片应力元件嵌入翅片。 翅片应力元件构造成促使平行于垂直方向的翅片内的垂直压缩力。 可选地,半导体材料包括硅,并且嵌入式翅片应力元件包括二氧化硅。

    HETEROGENEOUS CHANNEL MATERIAL INTEGRATION INTO WAFER
    18.
    发明公开
    HETEROGENEOUS CHANNEL MATERIAL INTEGRATION INTO WAFER 审中-公开
    HETEROFLEXIBLE通道基因材料整合晶片

    公开(公告)号:EP3063788A1

    公开(公告)日:2016-09-07

    申请号:EP14766337.1

    申请日:2014-09-03

    摘要: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.