公开(公告)号：EP2380195B1

公开(公告)日：2018-09-12

申请号：EP10700798.1

申请日：2010-01-20

Applicant: Raytheon Company

Inventor： TABATABAIE, Kamal ,  DAVIS, Michael, S. ,  LAROCHE, Jeffrey, R. ,  KAPER, Valery, S. ,  BETTENCOURT, John, P.

IPC: H01L21/8258 ,  H01L23/485 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L21/8258 ,  H01L23/485 ,  H01L23/53238 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0922 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure having a substrate, a seed layer over the substrate; a silicon layer disposed on the seed layer; a transistor device in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer of TiN or TaN and a layer of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor and another one of the electrical contacts being electrically connected to the III-V device.

公开(公告)号：EP2521168B8

公开(公告)日：2018-01-10

申请号：EP12166646

申请日：2012-05-03

Applicant: IMEC VZW

Inventor： HOFFMANN THOMAS Y ,  CAYMAX MATTY ,  WALDRON NIAMH ,  HELLINGS GEERT

IPC: H01L21/8258 ,  H01L21/28 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/8258 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78

Abstract: Method for manufacturing a hybrid MOSFET device comprising a first and a second MOSFET having respectively a first and a second channel material. A III-V-on-insulator stack is manufactured on a second substrate which is subsequently bonded to a first substrate. The III-V layer (103) and the insulator layer are selectively removed in a first region (I, I'), thereby exposing a semiconductor layer (107, 108) of the first substrate. A first gate stack (109, 109') of the first MOSFET is formed on the exposed semiconductor layer (107, 108) in the first region. A second gate stack (109'') of the second MOSFET is formed on the III-V layer (103) in the second region (II).

公开(公告)号：EP3008751A4

公开(公告)日：2017-03-15

申请号：EP14791900

申请日：2014-05-05

Applicant: TEXAS INSTRUMENTS INC

Inventor： TIPIRNENI NAVEEN ,  PENDHARKAR SAMEER ,  WISE RICK L

IPC: H01L21/8258 ,  H01L21/18

CPC classification number: H01L21/187 ,  H01L21/76254 ,  H01L21/8258

公开(公告)号：EP2805352A4

公开(公告)日：2015-09-09

申请号：EP13738701

申请日：2013-01-18

Applicant: SKORPIOS TECHNOLOGIES INC

Inventor： DALLESASSE JOHN ,  KRASULICK STEPHEN B ,  CREAZZO TIMOTHY ,  MARCHENA ELTON

IPC: H01L27/12 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06

CPC classification number: H01L27/14689 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/12 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/15

Abstract: A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

公开(公告)号：EP2494594A4

公开(公告)日：2014-05-28

申请号：EP10826485

申请日：2010-09-29

Applicant: SEMICONDUCTOR ENERGY LAB

Inventor： YAMAZAKI SHUNPEI ,  IMAI KEITARO ,  KOYAMA JUN

IPC: H01L21/8234 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/00 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H03K19/20

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

公开(公告)号：EP2255387A1

公开(公告)日：2010-12-01

申请号：EP09722679.9

申请日：2009-02-09

Applicant: Cree, Inc.

Inventor： SHEPPARD, Scott T.

IPC: H01L21/8252 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L27/0605 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/20 ,  H01L29/2003 ,  H01L29/7787 ,  H03H3/08 ,  H03H9/02228 ,  H03H9/02574 ,  H03H9/02976 ,  H03H9/0542

Abstract: Monolithic electronic devices including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first type of nitride device, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. A first plurality of electrical contacts are provided on the first at least one implanted n-type region. The first plurality of contacts define a first electronic device of the first type of nitride device. A second plurality of electrical contacts are provided on the second at least one n-type implanted region. The second plurality of contacts define a second electronic device of the second type of electronic device. Corresponding methods are also disclosed.

公开(公告)号：EP1358681A4

公开(公告)日：2008-04-30

申请号：EP02714683

申请日：2002-01-03

Applicant: UNIV MISSISSIPPI

Inventor： CASADY JEFFREY B ,  MAZZOLA MICHAEL

IPC: H01L21/04 ,  H01L21/76 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/24 ,  H01L29/49 ,  H01L29/732 ,  H01L29/786 ,  H01L29/80 ,  H01L29/812 ,  H01L31/0312 ,  H01L29/76

CPC classification number: H01L29/78603 ,  H01L21/0445 ,  H01L21/7602 ,  H01L21/8258 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/4908 ,  H01L29/732 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/802 ,  H01L29/812 ,  Y10S438/917 ,  Y10S438/931

Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

公开(公告)号：EP1411637A3

公开(公告)日：2004-07-21

申请号：EP03023559.2

申请日：2003-10-15

Applicant: Altera Corporation

Inventor： Kapoor, Ashok K.

IPC: H03K19/173 ,  H01L21/8258

CPC classification number: H03K19/173 ,  H01L27/118

Abstract: A programmable logic device (PLD) includes programmable electronic circuitry. The programmable electronic circuitry, fabricated in a silicon substrate, may include a variety of configurable or programmable logic circuitry. The PLD also includes a memory circuitry coupled to the programmable electronic circuitry. The memory circuitry is fabricated using silicon-germanium.

公开(公告)号：EP4498424A1

公开(公告)日：2025-01-29

申请号：EP24188556.5

申请日：2024-07-15

Applicant: STMicroelectronics International N.V.

Inventor： DEPETRO, Riccardo

IPC: H01L21/8258 ,  H01L21/02 ,  H01L27/06 ,  H01L27/085

Abstract: For manufacturing a semiconductor electronic device (1) a wafer (100) is provided which has a substrate layer (18) of semiconductor material having a first portion (101A) and a second portion (101B) distinct from the first portion. An epitaxial region (23, 106) of a single semiconductor material is grown on the first portion (101A) of the substrate layer. An epitaxial multilayer (49, 114) having a heterostructure (50) is grown on the second portion (101B) of the substrate layer. A first electronic component (5A, 5B, 5C, 5D) based on the single semiconductor material is formed from the epitaxial region (23, 106) and a second electronic component (7) based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions (25A, 25B, 27, 29A, 29B, 31) in the epitaxial region (23), after the step of growing an epitaxial multilayer.

公开(公告)号：EP4315408A1

公开(公告)日：2024-02-07

申请号：EP22715332.7

申请日：2022-03-31

Applicant: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO

Inventor： VOLLMER, René ,  UCCELLI, Emanuele

IPC: H01L21/8258 ,  H01L25/065 ,  H01L21/98 ,  H01L21/56