SHIFT REGISTER AND DISPLAY DEVICE
    4.
    发明公开
    SHIFT REGISTER AND DISPLAY DEVICE 有权
    移位寄存器和显示装置

    公开(公告)号:EP2486569A4

    公开(公告)日:2016-03-02

    申请号:EP10822121

    申请日:2010-10-04

    IPC分类号: G11C19/28 G09G3/32 G09G3/36

    摘要: The shift register includes first to fourth flip-flops. A first clock signal which is in a first voltage state in a first period and in a second voltage state in second to fourth periods is input to the first flip-flop. A second clock signal which is in the first voltage state in the second period and in the second voltage state in the third period and the fourth period is input to the second flip-flop. A third clock signal which is in the second voltage state in the first, second, and fourth periods and in the first voltage state in the third period is input to the third flip-flop. A fourth clock signal which is in the second voltage state in the first and second periods and in the first voltage state in the fourth period is input to the fourth flip-flop.

    SEMICONDUCTOR DEVICE
    6.
    发明公开

    公开(公告)号:EP2491585A4

    公开(公告)日:2015-09-02

    申请号:EP10824778

    申请日:2010-09-27

    摘要: An objet of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明公开
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    HERSTELLUNGSVERFAHRENFÜRHALBLEITERBAUELEMENT

    公开(公告)号:EP2449593A4

    公开(公告)日:2015-06-03

    申请号:EP10793992

    申请日:2010-06-09

    摘要: Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.

    摘要翻译: 公开了一种制造具有氧化物半导体作为沟道形成区域的薄膜晶体管的方法。 该方法包括: 在栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成与所述氧化物半导体层接触的源电极层和漏极电极层,使得所述氧化物半导体层的至少一部分露出; 以及在氧化物半导体层上形成氧化物绝缘膜并与氧化物半导体层接触。 在形成氧化物绝缘膜之前,氧化物半导体的暴露部分可能在存在等离子体的情况下暴露于含氧气体。 该方法允许氧扩散到氧化物半导体层中,这有助于薄膜晶体管的优异特性。

    SEMICONDUCTOR DEVICE
    9.
    发明公开

    公开(公告)号:EP1886355A4

    公开(公告)日:2015-04-01

    申请号:EP06756864

    申请日:2006-05-25

    摘要: A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region of the transistor through an opening provided in the second insulating layer, a third insulating layer over the first conductive layer, and a second substrate over the third insulating layer. The transistor comprises a semiconductor layer, a second conductive layer, and a fourth insulating layer provided between the semiconductor layer and the second conductive layer. One or plural layers selected from the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer have a step portion which is provided so as not to overlap with the transistor.