公开(公告)号：EP2351038A2

公开(公告)日：2011-08-03

申请号：EP09818320.5

申请日：2009-09-28

申请人： Intel Corporation

发明人： BAINS, Kuljit S. ,  HALBERT, John

IPC分类号： G11C11/4093 ,  G11C11/4096 ,  G11C11/4063 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

公开(公告)号：EP4022521A1

公开(公告)日：2022-07-06

申请号：EP20856408.8

申请日：2020-08-25

申请人： Micron Technology, Inc.

发明人： MURPHY, Richard C. ,  HUSH, Glen E. ,  SUN, Honglin

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C11/406 ,  G11C11/4063

公开(公告)号：EP2539897B1

公开(公告)日：2020-03-18

申请号：EP10846798.6

申请日：2010-12-01

申请人： Rambus Inc.

发明人： TSERN, Ely ,  VOGELSANG, Thomas ,  HAMPEL, Craig ,  BEST, Scott

IPC分类号： G11C11/4074 ,  G11C11/4063 ,  G11C11/408 ,  G06F13/14

公开(公告)号：EP3020047A1

公开(公告)日：2016-05-18

申请号：EP13889007.4

申请日：2013-07-09

申请人： Hewlett Packard Enterprise Development LP

发明人： LESARTRE, Gregg B. ,  WHEELER, Andrew R.

IPC分类号： G11C11/4063 ,  G11C11/4093 ,  G11C7/10

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1072

摘要： Example embodiments relate to write flow control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus and a memory controller that comply with a data transfer standard. The memory module may include a write buffer to receive write commands from the interface to the memory bus. The write buffer may cause the write commands to be transmitted to the non-compliant memory technology using a communication protocol that does not comply with the data transfer standard. The memory module may include a flow control credit counter to monitor the capacity of the write buffer, and to provide a credit count to the memory controller that indicates the number of write commands that the write buffer can accept.

公开(公告)号：EP2783367A1

公开(公告)日：2014-10-01

申请号：EP12851067.4

申请日：2012-11-23

申请人： Conversant Intellectual Property Management Inc.

发明人： CHOI, Byoung Jin

IPC分类号： G11C11/34 ,  G11C11/4063

CPC分类号： H01L25/0657 ,  G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4097 ,  G11C29/023 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for organizing memory for a computer system including a plurality of memory devices (2, 39), connected to a logic device (1), particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device (1) having capability to analyze and compensate for differing delays to the stacked devices (2,3,4,5) stacking multiple dice divided into partitions serviced by multiple buses (21,22) connected to a logic die (1), to increase throughput between the devices (2,3) and logic (1) device allowing large scale integration of memory with self-healing capability.

公开(公告)号：EP2751808A1

公开(公告)日：2014-07-09

申请号：EP12827743.1

申请日：2012-08-27

申请人： Rambus Inc.

发明人： VOGELSANG, Thomas

IPC分类号： G11C11/4063 ,  G11C11/4091

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097

摘要： Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.

公开(公告)号：EP2539897A4

公开(公告)日：2014-01-01

申请号：EP10846798

申请日：2010-12-01

申请人： RAMBUS INC

发明人： TSERN ELY ,  VOGELSANG THOMAS ,  HAMPEL CRAIG ,  BEST SCOTT

IPC分类号： G11C11/4074 ,  G06F13/14 ,  G11C11/4063 ,  G11C11/408

CPC分类号： G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

摘要翻译： 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核心和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以按比例缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移动信号以适应不同模式下的核心接口使用的信令电压。

公开(公告)号：EP2195913A1

公开(公告)日：2010-06-16

申请号：EP08800289.4

申请日：2008-09-09

申请人： Mosaid Technologies Incorporated

发明人： PYEON, Hong, Beom

IPC分类号： H02M3/07 ,  G11C11/4063 ,  G11C7/12

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

摘要： An apparatus and a method for producing a boosted voltage using a plurality of charge pumps circuits, charge pump control signals and an active capacitive element of an active charge pump, wherein the capacitive element of the activated charge pump is charged in response to the input voltage to the charge pump and the charge pump signal.

公开(公告)号：EP2100306A4

公开(公告)日：2010-03-10

申请号：EP07855586

申请日：2007-12-18

申请人： MOSAID TECHNOLOGIES INC

发明人： KIM JIN-KI

IPC分类号： G11C7/10 ,  G06F12/00 ,  G06F13/14 ,  G11C7/20 ,  G11C11/4063 ,  G11C11/413

CPC分类号： G11C14/0018 ,  G11C11/005

公开(公告)号：EP1955333A4

公开(公告)日：2009-07-08

申请号：EP06817678

申请日：2006-11-30

申请人： MOSAID TECHNOLOGIES INC

发明人： OH HAKJUNE

IPC分类号： G11C8/16 ,  G11C8/12 ,  G11C11/4063

CPC分类号： G11C11/406 ,  G11C8/10

摘要： A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for low power consumption. The logically identical circuits can include wordline address predecoder circuits, where a high speed predecoder circuit is enabled during a normal operating mode and a slower low power predecoder circuit is enabled for self-refresh operations. During self-refresh operations, the high speed circuit can be decoupled from the power supply to minimize its current leakage.