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公开(公告)号：EP2583303A1
公开(公告)日：2013-04-24
申请号：EP11794972.7
申请日：2011-04-26
发明人： KIM, Jin-Ki
IPC分类号： H01L23/48 , H01L23/488 , H03K17/56 , H05K10/00 , G01R31/30
CPC分类号： H01L25/0657 , G11C5/02 , G11C8/12 , G11C29/702 , H01L23/481 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544
摘要： Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector (1634-1, 1634-2, 1634-3, 1634-4) for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal (1654). Also disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group (1604), a plurality of signal lines connected to the primary TSV group, a redundant TSV group (1608) and connection circuitry (1620B) responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group (1608).
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22.发明公开A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 审中-公开与桥设备的复合存储于连接分立存储装置WITH A SYSTEM
公开(公告)号：EP2345035A1
公开(公告)日：2011-07-20
申请号：EP09820146.0
申请日：2009-10-14
发明人： KIM, Jin-Ki , PYEON, Hong, Beom
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
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公开(公告)号：EP2002442B1
公开(公告)日：2010-11-10
申请号：EP07719433.0
申请日：2007-03-29
发明人： KIM, Jin-Ki
IPC分类号： G11C7/10 , G11C11/4193 , G11C16/00
CPC分类号： G11C7/1042 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C7/1021 , G11C16/10 , G11C16/32 , G11C2216/22 , G11C2216/24
摘要： A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.
摘要翻译： 一种闪存系统架构，具有串行连接的闪存设备以实现数据的高速编程。 数据的高速编程通过在系统中的存储器设备之间交错要编程的数据的页面来实现，使得不同页面的数据被存储在不同的存储器设备中。 内存控制器为每个内存设备发出程序命令。 当每个存储器设备接收到程序命令时，它开始编程操作或将命令传递给下一个存储器设备。 因此，闪存系统中的存储器件依次编程数据页，从而最小化将每页数据编程到闪存系统中的延迟。 存储器控制器可以执行损耗均衡算法以使每个存储器设备的耐久性最大化，或者为任何尺寸的数据优化编程性能和耐久性。
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公开(公告)号：EP2220653A1
公开(公告)日：2010-08-25
申请号：EP08865169.0
申请日：2008-12-19
发明人： PYEON, Hong Beom , KIM, Jin-Ki
IPC分类号： G11C16/30
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/12 , G11C16/30
摘要： Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
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25.发明公开ID GENERATION APPARATUS AND METHOD FOR SERIALLY INTERCONNECTED DEVICES 审中-公开ID生成装置和方法SERIAL ASSOCIATES
公开(公告)号：EP2122626A1
公开(公告)日：2009-11-25
申请号：EP07855449.0
申请日：2007-12-03
CPC分类号： G11C7/20 , G06F13/4291 , G11C7/10 , G11C7/1003 , G11C19/00 , G11C2029/4402
摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.
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公开(公告)号：EP2118903A1
公开(公告)日：2009-11-18
申请号：EP07855464.9
申请日：2007-12-04
发明人： OH, HakJune , PYEON, Hong Beom , KIM, Jin-Ki
CPC分类号： G11C16/08 , G11C7/10 , G11C7/1078 , G11C7/20
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
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27.发明公开
公开(公告)号：EP2100306A1
公开(公告)日：2009-09-16
申请号：EP07855586.9
申请日：2007-12-18
发明人： KIM, Jin-Ki
IPC分类号： G11C7/10 , G06F12/00 , G06F13/14 , G11C11/4063 , G11C11/413 , G11C7/20
CPC分类号： G11C14/0018 , G11C11/005
摘要： A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.
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公开(公告)号：EP2074623A1
公开(公告)日：2009-07-01
申请号：EP07800456.1
申请日：2007-08-20
发明人： KIM, Jin-Ki , OH, HakJune , PYEON, Hong Beom
CPC分类号： G06F13/4243 , G11C7/10 , G11C7/1042 , G11C7/20 , G11C8/06 , G11C8/10
摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.
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公开(公告)号：EP1932158A1
公开(公告)日：2008-06-18
申请号：EP06790773.3
申请日：2006-09-29
发明人： OH, HakJune , PYEON, Hong, Beom , KIM, Jin-Ki
IPC分类号： G11C11/4197 , G11C11/4093 , G11C11/4063 , G11C16/26
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译： 公开了一种用于控制对半导体存储器中的串行数据链路接口的输出端口的数据传输的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使存储器件能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储器组，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。
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公开(公告)号：EP1461811B1
公开(公告)日：2006-03-29
申请号：EP02781031.6
申请日：2002-12-05
IPC分类号： G11C15/04
摘要： A low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a pre search portion and a main search portion. After issuing a search command, a pre search operation is conducted on the pre search portion of the matchline. If the result of the pre search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of pre search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Pre search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the pre search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.
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