公开(公告)号：EP3132469A1

公开(公告)日：2017-02-22

申请号：EP15718725.3

申请日：2015-04-10

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  KIM, Chin-Kwan ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC分类号： H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

摘要： An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

摘要翻译： 公开了一种集成电路（IC）衬底，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在电介质层和第二图案化金属层上形成非导电层。

公开(公告)号：EP3114707A1

公开(公告)日：2017-01-11

申请号：EP15710373.0

申请日：2015-03-04

申请人： Qualcomm Incorporated

发明人： KIM, Dong Wook ,  WE, Hong Bok ,  LEE, Jae Sik ,  GU, Shiqun

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

摘要： An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) coupled to a first surface of the base portion, and an underfill (222) between the first die and the base portion. The base portion includes a dielectric layer (202), and a set of redistribution metal layers (230-260). In some implementations, the integrated device further includes an encapsulation material (220) that encapsulates the first die. In some implementations, the integrated device further includes a second die (208) coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects (280) on the base portion, the set of interconnects coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars (216) and the second die includes a second set of interconnect pillars (218).

摘要翻译： 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基座部分，耦合到基部部分的第一表面的第一裸片以及在第一裸片与基部之间的底部填充。 基部包括电介质层和一组再分布金属层。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二模具。 在一些实施方案中，集成器件还包括在基部上的一组互连，该组互连电连接第一管芯和第二管芯。 在一些实施方案中，第一管芯包括第一组互连柱，并且第二管芯包括第二组互连柱。

公开(公告)号：EP3105787A1

公开(公告)日：2016-12-21

申请号：EP15706345.4

申请日：2015-02-11

申请人： Qualcomm Incorporated

发明人： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC分类号： H01L23/498 ,  H01L25/10

CPC分类号： H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

摘要： Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

公开(公告)号：EP3063790A1

公开(公告)日：2016-09-07

申请号：EP14793972.2

申请日：2014-10-28

申请人： Qualcomm Incorporated

发明人： KIM, Chin-Kwan ,  BCHIR, Omar James ,  KIM, Dong Wook ,  WE, Hong Bok

IPC分类号： H01L23/538 ,  H01L25/065

CPC分类号： H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

摘要： Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

摘要翻译： 一些新颖的特征涉及包括第一介电层和桥结构的衬底。 桥结构嵌入第一电介质层。 桥结构被配置为提供第一管芯和第二管芯之间的电连接。 第一和第二管芯被配置为耦合到衬底。 桥结构包括第一组互连和第二介电层。 第一组互连嵌入在第一电介质层中。 在一些实现中，桥结构还包括第二组互连。 在一些实施方案中，第二介电层被嵌入在第一介电层中。 一些实现方式，第一介电层包括桥结构的第一组互连，桥结构中的第二组互连，以及桥结构中的一组焊盘。

公开(公告)号：EP3053188A1

公开(公告)日：2016-08-10

申请号：EP14790822.2

申请日：2014-09-26

申请人： Qualcomm Incorporated

发明人： KIM, Dong Wook ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  YUN, Changhan Hobie

IPC分类号： H01L23/16 ,  H01L23/00

CPC分类号： H01L21/52 ,  H01L21/4817 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package (200). A continuous or uninterrupted stiffener structure (208) is designed with a recessed groove (208b), such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate (202) using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices (204) that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

公开(公告)号：EP2954555A2

公开(公告)日：2015-12-16

申请号：EP14703762.6

申请日：2014-01-31

申请人： Qualcomm Incorporated

发明人： GU, Shiqun ,  ZHANG, Rongtian ,  RAMACHANDRAN, Vidhya ,  KIM, Dong Wook

IPC分类号： H01L23/552 ,  H01L23/64 ,  H01L43/02 ,  H01L27/22

摘要： Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.