公开(公告)号：EP3338303A1

公开(公告)日：2018-06-27

申请号：EP16730956.6

申请日：2016-06-03

申请人： Qualcomm Incorporated

发明人： GU, Shiqun ,  WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook

IPC分类号： H01L23/538

CPC分类号： H01L23/5385 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

摘要： An integrated device package includes a first die, a second die, an encapsulation portion coupled to the first die and the second die, and a redistribution portion coupled to the encapsulation portion. The encapsulation portion includes an encapsulation layer, a bridge, and a first via. The bridge is at least partially embedded in the encapsulation layer. The bridge is configured to provide a first electrical path for a first signal between the first die and the second die. The first via is in the encapsulation layer. The first via is coupled to the bridge. The first via and the bridge are configured to provide a second electrical path for a second signal to the first die. The redistribution portion includes at least one dielectric layer, and at least one interconnect, in the dielectric layer, coupled to the first via.

公开(公告)号：EP3063790B1

公开(公告)日：2018-06-13

申请号：EP14793972.2

申请日：2014-10-28

申请人： Qualcomm Incorporated

发明人： KIM, Chin-Kwan ,  BCHIR, Omar James ,  KIM, Dong Wook ,  WE, Hong Bok

IPC分类号： H01L23/538 ,  H01L25/065

CPC分类号： H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

摘要： Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

公开(公告)号：EP3146562A1

公开(公告)日：2017-03-29

申请号：EP15725963.1

申请日：2015-05-18

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook

IPC分类号： H01L23/498 ,  H01L23/50

CPC分类号： H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

摘要： A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

摘要翻译： 提供封装基板，其包括核心基板和嵌入在包括第一侧的核心基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 该封装还包括在核心基板中横向延伸的第一电源金属板。 第一电源金属板从核心基板的第一侧直接设置在电容器的第一电极上。 第一通孔垂直于第一金属板延伸并且从核心基板的第一侧连接到第一电源金属板。

公开(公告)号：EP3140861A1

公开(公告)日：2017-03-15

申请号：EP15723397.4

申请日：2015-05-05

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun ,  RADOJCIC, Ratibor

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC分类号： H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

摘要： A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

摘要翻译： 提供了具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：EP3140860A1

公开(公告)日：2017-03-15

申请号：EP15719392.1

申请日：2015-04-17

申请人： Qualcomm Incorporated

发明人： GU, Shiqun ,  RADOJCIC, Ratibor ,  KIM, Dong Wook ,  LEE, Jae Sik

IPC分类号： H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/10 ,  H01L21/60

CPC分类号： H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

摘要： An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) (e.g., first wafer level die), and a second die (208) (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer (203), a first set of interconnects (280) located in the first inorganic dielectric layer, a second dielectric layer (202) different from the first inorganic dielectric layer, and a set of redistribution metal layers (230,240,250,260) in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects (280).

摘要翻译： 一些新颖的特征涉及在集成的装置（例如，集成的封装）那样包括用于集成装置，第一对（例如，第一晶片级模）的基部，和一个第二即（E. G.，第二晶片级模）。 基座部分包括第一无机介电层，第一组位于所述第一无机介电层中的互连，第二介电层从所述第一无机介电层不同，并且所述第二介电层中的一组再分布金属层。 第一个是连接到所述底座部分的第一表面上。 第二，其耦合到所述底座部分的第一表面，第二个是电通过所述第一组互连耦合到所述第一。

公开(公告)号：EP3140839A2

公开(公告)日：2017-03-15

申请号：EP15719383.0

申请日：2015-04-16

申请人： Qualcomm Incorporated

发明人： SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  KIM, Dong Wook ,  ZHANG, Xiaonan ,  LANE, Ryan David

IPC分类号： H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H01G4/236 ,  H01L49/02 ,  H05K1/16 ,  H01G2/10 ,  H05K1/18

CPC分类号： H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

摘要： Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

摘要翻译： 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：EP3074992A1

公开(公告)日：2016-10-05

申请号：EP14802564.6

申请日：2014-11-06

申请人： Qualcomm Incorporated

发明人： YUN, Changhan Hobie ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook

IPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/12

CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/12

摘要： An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.

摘要翻译： 一种装置包括两端MLCC。 双端MLCC包括导电层，其中导电层包括至少一个槽。 该装置还可以包括第二导电层，其包括至少一个槽和分离两个导电层的绝缘层。 在一个示例中，双端子MLCC的第一（例如，正）端子由第一组板形成，其中第一组中的每个板包括至少一个槽。 双端子MLCC的第二（例如负极）端子由第二组板形成，其中第二组中的每个板还包括至少一个槽。 第一组板和第二组板被交错，并且每对板由绝缘层分开。

公开(公告)号：EP3140839B1

公开(公告)日：2018-05-23

申请号：EP15719383.0

申请日：2015-04-16

申请人： Qualcomm Incorporated

发明人： SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  KIM, Dong Wook ,  ZHANG, Xiaonan ,  LANE, Ryan David

IPC分类号： H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H01G4/236 ,  H01L49/02 ,  H05K1/16 ,  H01G2/10 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC分类号： H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

摘要： Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

公开(公告)号：EP3216055A1

公开(公告)日：2017-09-13

申请号：EP15794782.1

申请日：2015-11-05

申请人： Qualcomm Incorporated

发明人： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook ,  GU, Shiqun

IPC分类号： H01L23/538

CPC分类号： H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162

摘要： Some novel features pertain to an integrated device package that includes an encapsulation portion and a redistribution portion. The encapsulation portion includes a first die, a first set of vias coupled to the first die, a second die, a second set of vias coupled to the second die, a bridge, and an encapsulation layer. The bridge is configured to provide an electrical path between the first die and the second die. The bridge is coupled to the first die through the first set of vias. The bridge is further coupled to the second die through the second set of vias. The encapsulation layer at least partially encapsulates the first die, the second die, the bridge, the first set of vias, and the second set of vias. The redistribution portion is coupled to the encapsulation portion. The redistribution portion includes a set of redistribution interconnects, and at least one dielectric layer.

摘要翻译： 一些新颖的特征涉及包括封装部分和再分布部分的集成器件封装。 封装部分包括第一裸片，耦合到第一裸片的第一组通孔，第二裸片，耦合到第二裸片的第二组通孔，桥和封装层。 桥被配置为在第一管芯和第二管芯之间提供电路径。 桥通过第一组通孔耦合到第一管芯。 该桥通过第二组通孔进一步耦合到第二管芯。 封装层至少部分封装第一管芯，第二管芯，桥，第一组通孔和第二组通孔。 再分布部分连接到封装部分。 再分布部分包括一组再分布互连和至少一个介电层。

公开(公告)号：EP3108504A1

公开(公告)日：2016-12-28

申请号：EP15706103.7

申请日：2015-02-06

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  KIM, Dong Wook ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC分类号： H01L23/498 ,  H01L23/50

CPC分类号： H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

摘要： An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

摘要翻译： 嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。 衬底包括外部电力网络。