公开(公告)号：EP2705572A4

公开(公告)日：2014-11-26

申请号：EP12779473

申请日：2012-04-27

申请人： INTEL CORP

发明人： KAMGAING TELESPHOR

IPC分类号： H01Q21/12 ,  H01L23/00 ,  H01L23/552 ,  H01Q1/12 ,  H01Q3/26 ,  H01Q21/00 ,  H01Q21/06

CPC分类号： H01Q1/1271 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01Q1/2283 ,  H01Q3/26 ,  H01Q21/0087 ,  H01Q21/0093 ,  H01Q21/065 ,  Y10T29/49016 ,  H01L2924/00

摘要： A glass-based, high-performance 60 GHz/mm-wave antenna includes cavities disposed in a phased-array antenna (PAA) substrate. The cavities are disposed below planar antenna elements. Emitter traces are disposed on the PAA substrate opposite the planar antenna elements and the emitter traces, the cavities, and the planar antenna elements are vertically aligned.

公开(公告)号：EP2732465A2

公开(公告)日：2014-05-21

申请号：EP12741161.9

申请日：2012-07-11

申请人： Invensas Corporation

发明人： HABA, Belgacem ,  ZOHNI, Wael ,  CRISP, Richard, Dewitt ,  MOHAMMED, Ilyas

IPC分类号： H01L25/065 ,  H01L23/13 ,  H01L23/49

CPC分类号： H01L23/481 ,  G11C5/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/061 ,  H01L2224/091 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic package 510 can include a substrate 520 having first and second opposed surfaces 521, 527, at least two pairs of microelectronic elements 507a, 512b, and a plurality of terminals 525 exposed at the second surface. Each pair of microelectronic elements 507 can include an upper microelectronic element 530b and a lower microelectronic element 530a. The pairs of microelectronic elements 507 can be fully spaced apart from one another in a horizontal direction H parallel to the first surface 521 of the substrate 520. Each lower microelectronic element 530a can have a front surface 531 and a plurality of contacts 535 at the front surface. A surface 531 of each of the upper microelectronic elements 530b can at least partially overlie the first surface 521 of the substrate 520 and the lower microelectronic element 530a in its pair.

公开(公告)号：EP2705572A2

公开(公告)日：2014-03-12

申请号：EP12779473.3

申请日：2012-04-27

申请人： Intel Corporation

发明人： KAMGAING, Telesphor

IPC分类号： H01Q21/12

CPC分类号： H01Q1/1271 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L2223/6677 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01Q1/2283 ,  H01Q3/26 ,  H01Q21/0087 ,  H01Q21/0093 ,  H01Q21/065 ,  Y10T29/49016 ,  H01L2924/00

摘要： A glass-based, high-performance 60 GHz/ mm-wave antenna includes cavities disposed in a phased-array antenna (PAA) substrate. The cavities are disposed below planar antenna elements. Emitter traces are disposed on the PAA substrate opposite the planar antenna elements and the emitter traces, the cavities, and the planar antenna elements are vertically aligned.

公开(公告)号：EP2585842A1

公开(公告)日：2013-05-01

申请号：EP11701720.2

申请日：2011-01-18

申请人： Xilinx, Inc.

发明人： RAHMAN, Arifur

IPC分类号： G01R31/28 ,  H01L21/66 ,  H01L25/065

CPC分类号： G01R31/318513 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/20 ,  H01L22/22 ,  H01L22/32 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

公开(公告)号：EP2543064A1

公开(公告)日：2013-01-09

申请号：EP10774342.9

申请日：2010-10-15

申请人： Xilinx, Inc.

发明人： RAHMAN, Arifur ,  MURALI, Venkatesan

IPC分类号： H01L21/98 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/68 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2902 ,  H01L2224/29187 ,  H01L2224/30181 ,  H01L2224/30183 ,  H01L2224/32137 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

摘要翻译： 集成电路（IC）将具有第一片上互连结构的第一IC芯片（芯片）和具有第二片上互连结构的第二IC芯片组合在重建的晶片基座上。 第二IC芯片与氧化物到氧化物边缘接合边缘接合到第一IC芯片。 芯片到芯片的互连结构电耦合第一IC芯片和第二IC芯片。

公开(公告)号：EP3329512A1

公开(公告)日：2018-06-06

申请号：EP16751411.6

申请日：2016-07-28

申请人： Qualcomm Incorporated

发明人： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC分类号： H01L21/60 ,  H01L23/538 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

摘要： A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

公开(公告)号：EP2924729A8

公开(公告)日：2016-02-24

申请号：EP15155426.8

申请日：2015-02-17

申请人： Intel Corporation

发明人： Chase, Harold Ryan ,  Manusharow, Mathew J. ,  Roy, Mihir K.

IPC分类号： H01L23/538 ,  H01L25/065

CPC分类号： H01L25/0652 ,  H01L21/56 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/83005 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18162 ,  H05K1/183 ,  H05K1/186 ,  H01L2924/00

摘要： Some embodiments relate to an electronic package. The electronic package includes a substraten (11) that includes a plurality of buildup layers (12A,12B,12C). A first die (13) is embedded in one of the buildup layers on one side of the substrate. A second die(16) is bonded to the substrate within a cavity (17) on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.

摘要翻译： 一些实施例涉及对电子封装。 所述电子封装包括衬底（11）做了包括堆积层（12A，12B，12C）的复数。 第一即（13）被嵌入在基板的一侧上的堆积层中的一个。 第二，在（16）在相对的基板的侧面结合到上的空腔（17）内的基材。 所述第一和第二所述的可电连接到导体堆积层的多元性内。 其它实施例涉及的第一连接到第二所述的，以形成电子封装的方法。 该方法包括：附接第一到一个芯和在芯上制造的衬底。 该方法包括在相对的基板侧和将第二对所述腔内的基板形成空腔在另一个堆积层的进一步上。

公开(公告)号：EP2904639A1

公开(公告)日：2015-08-12

申请号：EP13779700.7

申请日：2013-10-08

申请人： Qualcomm Incorporated

发明人： HE, Dongming ,  BAO, Zhongping ,  HUANG, Zhenyu

IPC分类号： H01L25/065 ,  H01L23/495

CPC分类号： H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

摘要： A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate (514), a level-one IC die (502) and a plurality of level-two IC dies (512a, 512b). The level-one IC die having a surface that is electrically coupled (520) to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled (516,518) to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

公开(公告)号：EP2732466A1

公开(公告)日：2014-05-21

申请号：EP12741420.9

申请日：2012-07-10

申请人： Tessera, Inc.

发明人： CRISP, Richard Dewitt ,  HABA, Belgacem ,  ZOHNI, Wael

IPC分类号： H01L25/065 ,  G11C5/06

CPC分类号： H01L23/48 ,  G11C5/06 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/29 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A microelectronic package (10) may have a plurality of terminals (36) disposed at a face (32) thereof which are configured for connection to at least one external component, e.g., a circuit panel (70). First and second microelectronic elements (12), (14) can be affixed with packaging structure (30) therein. A first electrical connection (51A, 40A, 74A) can extend from a respective terminal (36A) of the package (10) to a corresponding contact (20A) on the first microelectronic element (12), and a second electrical connection (53A, 40B, 52A) can extend from the respective terminal (36A) to a corresponding contact (26A) on the second microelectronic element (14), the first and second connections being configured such that a respective signal carried by the first and second connections is subject to propagation delay of the same duration between the respective terminal (36A) and each of the corresponding contacts (20A, 26A) coupled thereto.

公开(公告)号：EP2709144A2

公开(公告)日：2014-03-19

申请号：EP13183374.1

申请日：2013-09-06

申请人： Freescale Semiconductor, Inc.

发明人： Leal, George R ,  Pham, Tim V

IPC分类号： H01L21/56 ,  H01L23/433 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

摘要翻译： 提供了一种用于制造具有暴露的散热器盖阵列（310）的基于引线框架的热增强倒装芯片封装的方法和设备，所述裸露散热器盖阵列（310）通过包括热界面粘附层（308）而被设计用于直接附接到集成电路裸片（306） ）到除了散热器盖（312）的平坦上盖表面之外的每个管芯（306）并且用附接模制化合物（321）封装附接的散热器盖阵列（310）和集成电路管芯阵列（306）。