公开(公告)号：EP2334589B1

公开(公告)日：2013-02-20

申请号：EP09787279.0

申请日：2009-09-24

Applicant: NXP B.V.

Inventor： ROOZEBOOM, Freddy c/o NXP Semiconductors Betchworth House ,  GOOSSENS, Martijn c/o NXP Semiconductors Betchworth House ,  BESLING, Willem Frederik Adrianus c/o NXP Semiconductors Betchworth House ,  VERHAEGH, Nynke c/o NXP Semiconductors Betchworth House

IPC: B81B1/00 ,  B81B3/00 ,  H01L29/41 ,  H01L31/0224

CPC classification number: H01L29/41 ,  B81B3/007 ,  B81B2201/06 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L28/91

公开(公告)号：EP1800334A2

公开(公告)日：2007-06-27

申请号：EP05789502.1

申请日：2005-10-04

Applicant: Silverbrook Research Pty. Ltd

Inventor： MCREYNOLDS, Darrell LaRue ,  SILVERBROOK, Kia

IPC: H01L21/3065

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A method of polymeric coating from sidewalls of en etched trench defined in silicon wafer [5] was provided The method comprises etching the wafer in a biased plasma etching chamber using 02 plasma. The chamber temperature is in the range of 90-180 deg C.

公开(公告)号：EP1435336A2

公开(公告)日：2004-07-07

申请号：EP03023819.0

申请日：2003-10-20

Applicant: ROBERT BOSCH GMBH

Inventor： Lutz, Markus ,  Partridge, Aaron

IPC: B81C1/00

CPC classification number: B81C1/00063 ,  B81B3/0086 ,  B81C2201/0112 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A method for adjusting with high precision the width of gaps between micromachined structures or devices in an epitaxial reactor environment. Providing a partially formed micromechanical device, comprising a substrate layer, a sacrificial layer including silicon dioxide deposited or grown on the substrate and etched to create desired holes and/or trenches through to the substrate layer, and a function layer deposited on the sacrificial layer and the exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Cleaning residues from the surface of the device, then epitaxially depositing a layer of gap narrowing material selectively on the surfaces of the device. The selection of deposition surfaces determined by choice of materials and the temperature and pressure of the epitaxy carrier gas. The gap narrowing epitaxial deposition continues until a desired gap width is achieved, as determined by, for example, an optical detection arrangement. Following the gap narrowing step, the micromachined structures or devices may be released from their respective underlying sacrificial layer.

Abstract translation: 一种用于在外延反应器环境中高精度调整微加工结构或器件之间的间隙的宽度的方法。 提供部分形成的微机械装置，其包括衬底层，牺牲层，包括沉积或生长在衬底上并被蚀刻以形成通向衬底层的所需孔和/或沟槽的二氧化硅;以及沉积在牺牲层上的功能层， 衬底层的暴露部分，然后蚀刻以在其中限定微机械结构或器件。 蚀刻工艺使除去的功能层材料下方的牺牲层露出。 从装置的表面清洁残留物，然后在装置的表面上选择性地外延地沉积间隙变窄材料层。 通过选择材料和外延载气的温度和压力来确定沉积表面的选择。 缩小外延沉积的间隙持续到通过例如光学检测装置确定的达到期望的间隙宽度为止。 在间隙变窄步骤之后，微加工结构或器件可以从它们各自的底层牺牲层释放。

公开(公告)号：EP0865664A1

公开(公告)日：1998-09-23

申请号：EP97911131.0

申请日：1997-10-06

Applicant: ROBERT BOSCH GMBH

Inventor： LÄRMER, Franz ,  SCHILP, Andrea

IPC: B81C1 ,  C23F4 ,  H01L21

CPC classification number: H01L21/465 ,  B81C1/00619 ,  B81C2201/0112 ,  C23F4/00 ,  H01L21/30655

Abstract: The invention concerns a process for producing etched structures in substrates by means of anisotropic plasma etching. An isotropic etching operation and a side wall passivation are carried out in separate and alternating operations. The substrate (2) is a polymer, a metal, or a multi-component system and portions (8) of the side wall passivation layer (6) applied during the side wall passivation are transferred to the exposed lateral surfaces (7') of the side wall (7) during each subsequent etching operations as a result of which the entire process becomes anisotropic.

公开(公告)号：EP0683921A4

公开(公告)日：1997-01-02

申请号：EP94903348

申请日：1993-12-03

Applicant: CORNELL RES FOUNDATION INC

Inventor： SHAW KEVIN A ,  ZHANG Z LISA ,  MACDONALD NOEL C

IPC: C23F4/00 ,  B81B3/00 ,  G01P15/08 ,  G01P15/125 ,  H01L21/302 ,  H01L21/3065 ,  H01L29/82 ,  H01L29/84 ,  H01L21/44 ,  H01L21/449 ,  H01L23/48 ,  H01L29/06 ,  H01L29/86 ,  H01L29/96

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

公开(公告)号：EP0625285A1

公开(公告)日：1994-11-23

申请号：EP94900729.0

申请日：1993-11-27

Applicant: ROBERT BOSCH GMBH

Inventor： LAERMER, Franz ,  SCHILP, Andrea

IPC: H01L21 ,  B81C1

CPC classification number: H01L21/3085 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L21/30655 ,  Y10T428/24521

Abstract: L'invention concerne un procédé d'attaque anisotrope de structures délimitées avec un masque d'attaque, de préférence des évidements dont les côtés sont exactement délimités, au moyen d'un plasma. Selon ce procédé, on obtient à la fois une sélectivité élevée du masque et une très forte anisotropie des structures attaquées. A cet effet, ce procédé d'attaque anisotrope comprend les opérations successives séparées et alternées de polymérisation et d'attaque.

公开(公告)号：EP2829512B1

公开(公告)日：2018-03-07

申请号：EP14177859.7

申请日：2014-07-21

Applicant: Atlantic Inertial Systems Limited

Inventor： Hawke, Tracey ,  Venables, Mark ,  Sturland, Ian ,  Eley, Rebecka

IPC: B81C1/00

CPC classification number: B81C1/00531 ,  B81B3/0064 ,  B81B2201/033 ,  B81B2203/033 ,  B81C1/00388 ,  B81C1/00619 ,  B81C2201/0112 ,  H01L21/3065 ,  H01L21/308

Abstract: A method of reactive ion etching a substrate 46 to form at least a first and a second etched feature (42, 44) is disclosed. The first etched feature (42) has a greater aspect ratio (depth:width) than the second etched feature (44). In a first etching stage the substrate (46) is etched so as to etch only said first feature (42) to a predetermined depth. Thereafter in a second etching stage, the substrate (46) is etched so as to etch both said first and said second features (42, 44) to a respective depth. A mask (40) may be applied to define apertures corresponding in shape to the features (42, 44). The region of the substrate (46) in which the second etched feature (44) is to be produced is selectively masked with a second maskant (50) during the first etching stage. The second maskant (50) is then removed prior to the second etching stage.

公开(公告)号：EP3055249A1

公开(公告)日：2016-08-17

申请号：EP14787234.5

申请日：2014-10-02

Applicant: Centre National de la Recherche Scientifique ,  Universite de Nantes

Inventor： LETHIEN, Christophe ,  TILMANT, Pascal ,  EUSTACHE, Etienne ,  ROLLAND, Nathalie ,  BROUSSE, Thierry

IPC: B81C1/00

CPC classification number: H01M10/02 ,  B81B1/002 ,  B81B2203/0315 ,  B81B2203/0361 ,  B81C1/00047 ,  B81C1/00111 ,  B81C2201/0112 ,  B81C2201/013 ,  B81C2201/0159 ,  H01G11/70 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0585 ,  H01M2220/30

Abstract: The invention relates to a microstructured substrate comprising a plurality of at least one elementary microstructure (3), and to the method for producing said microstructured substrate. Said at least one elementary microstructure (3) has a long shape and opposing longitudinal lower (3a) and upper (3b) ends, the lower end (3a) being connected to the substrate, and also comprises an open cavity (5) on the upper end (3b) thereof, said microstructured substrate comprising alumina on the surface thereof. The invention also relates to an electrical storage device, more specifically an all-solid battery, comprising the microstructured substrate according to the invention.

Abstract translation: 微结构化衬底包括多个至少一个基本微结构。 电存储装置，特别是全固态电池可以包括微结构化基板。

公开(公告)号：EP2091648A2

公开(公告)日：2009-08-26

申请号：EP07864582.7

申请日：2007-11-19

Applicant: Bioscale, Inc.

Inventor： MILLER, Michael ,  MASTERS, Brett P. ,  SCHMIDT, Martin

IPC: B01L3/00 ,  B81C1/00

CPC classification number: B81C1/00714 ,  B81B2201/058 ,  B81B2203/033 ,  B81C2201/0112

Abstract: The invention relates to fluid paths in etchable materials. Fluid paths are formed by forming a cavity through a substrate material with a first dry removal process to produce a first surface of the cavity. The first surface of the cavity is associated with a first roughness. The first surface of the cavity is etched with a second wet removal process to reduce the first roughness and produce a second roughness associated with the first surface of the cavity. A coating is applied to the first surface of the cavity to produce a second surface to improve wettability of the first or second surface of the cavity, reduce in size or number gas nucleation sites in the first or second surface of the cavity, reduce the amount of debris associated with the first roughness carried by the fluid flow, and/or improve hydrophilicity of the first or second surface.

公开(公告)号：EP2035328A1

公开(公告)日：2009-03-18

申请号：EP07728630.0

申请日：2007-04-27

Applicant: Robert Bosch GmbH

Inventor： LAERMER, Franz ,  STUMBER, Michael ,  FEYH, Ando ,  SCHOLTEN, Dick ,  MAEURER, Christian ,  CASSEMEYER, Julia

IPC: B81C1/00 ,  A61M37/00

CPC classification number: B81C1/00119 ,  A61M37/0015 ,  A61M2037/003 ,  A61M2037/0038 ,  A61M2037/0046 ,  A61M2037/0053 ,  B81C2201/0112 ,  B81C2201/0115

Abstract: The invention relates to a method for producing porous micro-needles (10) that are arranged on a silicon substrate (5) in an array, for the transdermal administration of medicaments and to the use of said micro-needles. Said method consists of the following steps, a silicon substrate (5) is prepared, a first etching mask is applied, micro-needles (10) are structured by means of a DRIE-process (deep reactive ion etching), the first etching mask is removed and the Si-substrate (5) is at least partially made porous. The porous making process starts on the front side (15) of the Si-substrate (5) and a porous reservoir is formed.