公开(公告)号：EP0634751A1

公开(公告)日：1995-01-18

申请号：EP94304644.1

申请日：1994-06-27

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: A memory includes a number of memory groups. Each memory group includes a set of memory subgroups and a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output. The true and complement inputs are connected to a memory subgroup by at least one sense amplifier. A true connection point also is included in the memory, and the true output of one of the data bus drivers from each of the memory groups are connected together at the connection point, and a "wired" configuration is created. In addition, the memory includes a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the connection point, creating a "wired" configuration. The memory also has a data bus circuit with a true input connected to the true connection point and a complement input connected to the complement connection point and a first circuit. This data bus circuit is responsive to signals from the true and complement connection points created by the simultaneous addressing of multiple groups or a subset of the memory subgroups in testing mode. The first circuit has an output for providing an indication of an error in addressing of the multiple groups or the subset of the memory subgroups.

Abstract translation: 存储器包括多个存储器组。 每个存储器组包括一组存储器子组和多个数据总线驱动器，其中每个数据总线驱动器具有真实输入和补码输入以及真实输出和补码输出。 真实和补码输入由至少一个读出放大器连接到存储器子组。 存储器中还包括真正的连接点，并且来自每个存储器组的一个数据总线驱动器的真实输出在连接点处连接在一起，并且创建“有线”配置。 此外，存储器包括补码连接点，其中来自每个存储器组的数据总线驱动器之一的补码输出在连接点处连接在一起，从而产生“有线”配置。 存储器还具有连接到真实连接点的真实输入的数据总线电路和连接到补码连接点的补码输入和第一电路。 该数据总线电路响应来自在测试模式下由同时寻址多个组或存储器子组的子集创建的真实和补充连接点的信号。 第一电路具有用于提供对多个组或存储器子组的子集的寻址中的错误的指示的输出。

公开(公告)号：EP0443070A1

公开(公告)日：1991-08-28

申请号：EP90103503.0

申请日：1990-02-23

Applicant: SCHEIDT & BACHMANN GMBH

Inventor： Ehl, Rolf Josef ,  Schürmans, Peter, Dipl.-Ing.

IPC: G06F12/06 ,  G06F11/20

CPC classification number: G11C29/28

Abstract: Die Erfindung betrifft eine Anordnung zum Prüfen der Funktionsfähigkeit von Speicherplätzen eines Schreib-Lese-Speichers (4a bzw. 4b) innerhalb eines Computers, dessen CPU (1) über einen Daten- und Adreßbus (2,3) mit dem Schreib-Lese-Speicher (4a bzw. 4b) verbunden ist. Um unabhängig vom Prozeßverlauf und auch bei Interrupt-Verarbeitung jederzeit und ohne zeitliche Beschränkung eine beliebig komplexe Prüfung des Schreib-Lese-Speichers (4a bzw. 4b) zu ermöglichen, wird eine der Anzahl der Speicherplätze entsprechende Anzahl von Speicherplätzen auf einem physikalisch getrennten Schreib-Lese-Speicher (4b bzw. 4a) zur Verfügung gestellt, der über denselben Daten- und Adreßbus (2,3) von derselben CPU (1) betrieben wird. Die Ansteuerung dieser Speicherplätze beider Schreib-Lese-Speicher (4a und 4b) erfolgt durch eine gemeinsame Steuerlogik (5) derart, daß beide Speicherbereiche als getrennt ansprechbare Speicher benutzbar sind, von denen wahlweise ein Speicherbereich als Arbeitsspeicher benutzt wird, während der andere Speicherbereich einem Prüfprogramm unterzogen wird. Hierbei erfolgen zwischen den zeitlich aufeinanderfolgenden Wechseln der beiden Speicherbereiche zu Arbeits- bzw. Testzwecken die Schreiboperationen der fortlaufend anfallenden Prozeßdaten parallel in beide Speicherbereiche. Leseoperationen erfolgen aber nur aus dem gerade als Arbeitsspeicher dienenden Speicherbereich, und zwar so lange, bis alle Daten aus dem jeweils als Arbeitsspeicher dienenden Speicherbereich in den getesteten Speicherbereich durch Auslesen und Wiederzurückschreiben des gesamten Arbeitsspeichervolumens mit Hilfe der CPU (1) übernommen worden sind.

Abstract translation: 本发明涉及一种在布置用于验证的读/写存储器的存储器位置的正确运行（图4a和4b）在计算机中，CPU（1）的所有连接到读/写存储器（4a和4b）通过 一个数据和地址总线（2，3）。 以提供读/写存储器的验证的可能性（4a和4b）任何在任何时间和没有处理运行的时间限制unabhängig甚至中断处理期间复杂的，对应于存储的数量的数量的存储位置 位置是在其中通过相同的数据和地址总线操作的物理上独立的读/写存储器（图4b和4a）所有可用（2,3）由相同的CPU（1）。 两个读这些存储位置/写存储器（4a和4b）由共同的控制逻辑（5）求的方式选择没有这两个存储区域可以作为分开使用可寻址存储器，其一个存储区域被任选地使用作为 而其他存储区域工作记忆经受验证程序。 在这种结构中，不断呈现的过程数据的写操作发生在工作和测试目的的两个存储区的老国家之间两个存储区并行继在时间上彼此。 然而，读取操作只能从记忆areaswhich好发是目前正在使用工作记忆，直到所有的数据都在每种情况下作为正常工作的内存测试存储区的存储区通过读出和回写的被转移 整个工作存储器量与CPU（1）的助剂。

公开(公告)号：EP0441088A1

公开(公告)日：1991-08-14

申请号：EP90480177.6

申请日：1990-10-31

Applicant: International Business Machines Corporation

Inventor： Eikill, Richard Glenn ,  Finnes, Steven John ,  Geer, Charles Porter ,  Schmierer, Quentin Gust

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: A data processing network includes multiple processing devices (18, 20), multiple memory cards (24, 26, 28) of main storage, and a main storage interface shared by the processors and memory cards. Each of the memory cards includes memory arrays (34, 46, 58), a hold register (32, 44, 56) for retaining a data pattern stored to the arrays, a compare register (36, 48, 60) and logic circuity (40, 52, 64). For a memory array diagnostic test, one of the processing devices sends a compare command (including address information) and the data pattern to one of the memory cards. In response, the logic circuity on the selected memory card stores the data pattern to its hold register and writes the data pattern into its memory arrays, then reads the data out of the memory arrays into its compare register. The contents of the compare and hold registers are compared, and an error indication provided to the processing device in the event that these registers' contents are not the same.

Abstract translation: 数据处理网络包括主存储器的多个处理设备（18,20），多个存储卡（24,26,28）以及由处理器和存储卡共享的主存储接口。 每个存储卡包括存储器阵列（34,46,58），用于保存存储到阵列的数据模式的保持寄存器（32,44,56），比较寄存器（36,48,60）和逻辑电路（ 40，52，64）。 对于存储器阵列诊断测试，其中一个处理设备向其中一个存储卡发送比较命令（包括地址信息）和数据模式。 作为响应，所选存储卡上的逻辑电路将数据模式存储到其保持寄存器，并将数据模式写入其存储器阵列中，然后将数据从存储器阵列读出到其比较寄存器中。 比较和保持寄存器的内容，并且在这些寄存器的内容不相同的情况下提供给处理设备的错误指示。

公开(公告)号：EP0440206A2

公开(公告)日：1991-08-07

申请号：EP91101223.5

申请日：1991-01-30

Applicant: NEC CORPORATION

Inventor： Mizukami, Takeshi

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C29/28

Abstract: A semiconductor memory comprises memory cell arrays and data amplifiers, four or more respectively, and two common read buses for them. Each data amplifier outputs the first and second data having respective levels complementary to each other. It further comprises the first and second logic circuits. Each logic circuit is composed of a plurality of transistors, each of which being located adjacent to the respective corresponding data amplifier, to the gate of each the first aid second data being applied, and the drain of each being connected to the two read buses. The semiconductor memory further comprises the third logic circuit into which the data from the two read buses are input. The number of data buses needed can be reduced to only three in total for write and read operations independent of the number of memory cell arrays, contributing to minimization of chip area.

Abstract translation: 半导体存储器包括分别为四个或更多个的存储单元阵列和数据放大器，以及用于它们的两个公共读总线。 每个数据放大器输出具有彼此互补的各自电平的第一和第二数据。 它还包括第一和第二逻辑电路。 每个逻辑电路由多个晶体管组成，每个晶体管各自位于相应的相应的数据放大器附近，被施加到每个急救第二数据的栅极，并且每个晶体管的漏极连接到两个读总线。 半导体存储器还包括输入来自两个读总线的数据的第三逻辑电路。 所需的数据总线的数量可以减少到只有三个写入和读取操作，独立于存储单元阵列的数量，有助于最小化芯片面积。

公开(公告)号：EP3254286A1

公开(公告)日：2017-12-13

申请号：EP16746987.3

申请日：2016-01-27

Applicant: Micron Technology, Inc.

Inventor： ZAWODNY, Jason T. ,  HUSH, Glen E. ,  MANNING, Troy A. ,  FINKBEINER, Timothy P.

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/12

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C5/025 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：EP3121679A2

公开(公告)日：2017-01-25

申请号：EP16180706.0

申请日：2016-07-22

Applicant: NXP USA, Inc.

Inventor： Sadd, Michael A ,  Roy, Anirban

IPC: G05F1/56 ,  G11C5/14 ,  H03K19/003

CPC classification number: H03J5/02 ,  G02F2203/48 ,  G11C5/147 ,  G11C29/021 ,  G11C29/28 ,  G11C29/50008 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/0629 ,  H03F3/45183 ,  H03F2203/45048 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45396 ,  H03F2203/45674 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K19/00369

Abstract: The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element (110) is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element (110) is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

公开(公告)号：EP2860635A1

公开(公告)日：2015-04-15

申请号：EP14190168.6

申请日：2008-03-27

Applicant: Violin Memory, Inc.

Inventor： Bennett, Jon C. R.

IPC: G06F11/10 ,  G11B20/18

CPC classification number: G06F3/065 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0866 ,  G11B20/1833 ,  G11B2220/60 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/28 ,  G11C29/52

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Abstract translation: 描述了一种存储系统及其操作方法，其中存储器系统用于以RAIDed方式存储数据。 可以检索存储的数据，包括奇偶校验数据，使得当已经接收到没有奇偶校验数据的所存储的数据中的第一个或来自除了一个存储器模块和奇偶校验数据的所有存储的数据之前，存储的数据被恢复。 对于低写入数据加载的数据写入被管理，使得在一段时间间隔内只有一个RAID条带的存储器模块被写入或擦除。

公开(公告)号：EP2132636A2

公开(公告)日：2009-12-16

申请号：EP08742320.8

申请日：2008-03-27

Applicant: Violin Memory, Inc.

Inventor： BENNETT, Jon, C. R.

IPC: G06F12/08 ,  G11B20/18

CPC classification number: G06F3/065 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0866 ,  G11B20/1833 ,  G11B2220/60 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/28 ,  G11C29/52

Abstract: A memory system and method of operating the same is described, where the memory systenris used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

公开(公告)号：EP1755128A2

公开(公告)日：2007-02-21

申请号：EP06118948.6

申请日：2006-08-15

Applicant: Saifun Semiconductors Ltd.

Inventor： Shappir, Assaf ,  Cohen, Guy ,  Lusky, Eli

IPC: G11C16/26

CPC classification number: G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50004

Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level of a group of history cells associated with a group of memory cells of a non-volatile memory cell array, allowing correct reading of the group of history cells, selecting a memory read reference level according to the first read reference level, and reading the non-volatile memory array cells.

Abstract translation: 一种方法包括根据不同组存储器单元的阈值电压分布的改变来改变用于读取一组存储器单元的读取参考电平。 改变步骤包括确定与非易失性存储器单元阵列的一组存储器单元相关联的一组历史存储单元的历史读取参考电平，允许正确读取该组历史存储单元，根据 第一读取参考电平以及读取非易失性存储器阵列单元。

公开(公告)号：EP0634751B1

公开(公告)日：2001-03-14

申请号：EP94304644.1

申请日：1994-06-27

Applicant: STMicroelectronics, Inc.

Inventor： McClure, David Charles

IPC: G11C29/00

CPC classification number: G11C29/28

Abstract: A memory includes a number of memory groups. Each memory group includes a set of memory subgroups and a number of data bus drivers, wherein each data bus driver has a true input and a complement input and a true output and a complement output. The true and complement inputs are connected to a memory subgroup by at least one sense amplifier. A true connection point also is included in the memory, and the true output of one of the data bus drivers from each of the memory groups are connected together at the connection point, and a "wired" configuration is created. In addition, the memory includes a complement connection point, wherein the complement output of one of the data bus drivers from each of the memory groups are connected together at the connection point, creating a "wired" configuration. The memory also has a data bus circuit with a true input connected to the true connection point and a complement input connected to the complement connection point and a first circuit. This data bus circuit is responsive to signals from the true and complement connection points created by the simultaneous addressing of multiple groups or a subset of the memory subgroups in testing mode. The first circuit has an output for providing an indication of an error in addressing of the multiple groups or the subset of the memory subgroups.