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    MOSFET manufacture
    21.
    发明公开
    MOSFET manufacture 失效
    MOSFET制造。

    公开(公告)号：EP0607658A2

    公开(公告)日：1994-07-27

    申请号：EP93308842.9

    申请日：1993-11-04

    申请人： AT&T Corp.

    发明人： Lee, Kuo-Hua ,  Liu, Chun-Ting ,  Steiner, Kurt George ,  Yu, Chen-Hua Douglas

    IPC分类号： H01L21/336 ,  H01L21/316 ,  H01L21/311 ,  H01L29/10

    CPC分类号： H01L29/66492 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L29/1083 ,  H01L29/6659

    摘要： A method of semiconductor integrated circuit fabrication including a technique for forming punch-through control implants (e.g., 37, 39) is disclosed. After gate (e.g., 13, 15) formation, a dielectric (e.g., 17) is formed which covers the gate (e.g., 13, 15) and exposed portions of a semiconductor substrate (e.g., 11). The dielectric is formed by a process which makes that portion of the dielectric adjacent the gate sidewalls more vulnerable to wet etching than those portions of the dielectric which are adjacent the top of the gate and the exposed substrate. The dielectric is then subsequently etched to form channels (e.g., 29, 31) adjacent the gate which exposed the substrate and served to collimate an ion (e.g., 35) implantation beam. The remaining portions of the dielectric may then be stripped away and conventional procedures employed to form source (e.g., 45) and drain (e.g., 47). Illustratively, the dielectric is formed from TEOS to which NF 3 is added during the deposition process. The addition of NF 3 makes that portion of the dielectric which forms adjacent the gate sidewalls particularly vulnerable to hydrofluoric acid etching while those portions of the dielectric covering the substrate and covering the gate (e.g., 13, 15) are not so vulnerable.

    Method for fabricating intermetal dielectric structures including air-gaps between metal leads
    28.
    发明公开
    Method for fabricating intermetal dielectric structures including air-gaps between metal leads 审中-公开
    维尔法赫恩zur Hestellung von Zwischenmetall-Dielektrikanwendungen mit Luftspalten zwischen Metall-Leitern

    公开(公告)号：EP1209739A3

    公开(公告)日：2004-02-11

    申请号：EP01480117.9

    申请日：2001-11-23

    申请人： CHARTERED SEMICONDUCTOR MANUFACTURING, INC.

    发明人： Lim, Victor Seng Keong ,  Teh, Young-Way ,  Ang, Ting-Cheong ,  See, Alex ,  Siew, Yong Kong

    IPC分类号： H01L21/768 ,  H01L21/312 ,  H01L21/764 ,  H01L23/532 ,  H01L23/522

    CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/7682

    摘要： A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol(PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the pexraeable dielectric layer.

    摘要翻译： 一种制造具有通过汽化填料聚合物材料形成气隙的金属化方案的方法。 填充材料被临界可渗透的介电层覆盖。 该方法通过在半导体结构上形成间隔的导线开始。 间隔开的导线具有顶表面。 在间隔开的导线和半导体结构之上形成填充材料。 填充材料优选由选自聚丙二醇（PPG），聚丁二烯（PB）聚乙二醇（PEG），氟化无定形碳和聚己内酯二醇（PCL）组成的组中的材料组成，并且通过旋涂工艺或 CVD工艺。 我们回蚀填充材料以暴露间隔开的导线的顶表面。 接下来，将半导体结构加载到HDPCVD室中。 在关键步骤中，在填充材料上形成可渗透介电层。 可渗透介电层具有允许分解的气相填充材料扩散通过的性质。 在另一个关键步骤中，我们将填充材料蒸发成将填料材料变成气相填料。 气相填充材料通过可渗透介电层扩散以在间隔开的导线之间形成间隙。 在可渗透的介电层上形成绝缘层。

    Method of forming low dielectric constant insulation film for semiconductor device
    30.
    发明公开
    Method of forming low dielectric constant insulation film for semiconductor device 审中-公开
    一种用于制造具有用于半导体器件的低介电常数的电介质膜的方法

    公开(公告)号：EP1256978A2

    公开(公告)日：2002-11-13

    申请号：EP02253261.8

    申请日：2002-05-09

    申请人： ASM JAPAN K.K.

    发明人： Matsuki, Nobuo ,  Umemoto, Seijiro ,  Hyoudo, Yasuyoshi

    IPC分类号： H01L21/316

    CPC分类号： H01J37/32522 ,  C23C16/509 ,  H01J37/32082 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31608

    摘要： A thin film having a low dielectric constant is formed on a semiconductor substrate by plasma reaction using a method including the steps of: (i) introducing a reaction gas into a reaction chamber for plasma CVD processing wherein a semiconductor substrate is placed on a lower stage; and (ii) forming a thin film on the substrate by plasma reaction while reducing or discharging an electric charge from the substrate surface. In the reaction chamber, an upper region for plasma excitation and a lower region for film formation on the substrate are formed. An intermediate electrode is used to divide the interior of the reaction chamber into the upper region and the lower region. The discharge can also be conducted by lowering the temperature of the lower stage to condense moisture molecules on the substrate surface, especially by using a cooling plate disposed between the intermediate electrode and the lower stage.

    摘要翻译： 具有低介电常数的薄膜是形成在由等离子体反应，使用一种方法，包括的步骤的半导体衬底：（i）将反应气体引入worin一个半导体衬底上的下段放置等离子体CVD处理的反应室 ; 和（ii）由等离子体反应形成在基板上的薄膜，同时减少或从表面基材电荷的放电。 在用于等离子体激发上部区域中的反应室和用于在基片上成膜的下部区域中形成。 中间电极被用来划分反应室到上部区域的内部和下部区域中。 放电因此，可以通过降低下阶段的温度凝结在基板表面的水分的分子中进行，通过使用中间电极与所述下段之间设置一冷却板爱更是如此。