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公开(公告)号：EP4239686A1
公开(公告)日：2023-09-06
申请号：EP23159048.0
申请日：2023-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： IUCOLANO, Ferdinando , CHINI, Alessandro
IPC: H01L29/778 , H01L21/338 , H01L21/336 , H01L29/423 , H01L29/417 , H01L29/20
Abstract: The HEMT device (50) is formed by a heterostructure (62), by an insulation layer (68) that extends on the heterostructure and has a thickness along a first direction (Z), and by a gate region (74). The gate region has a first portion (74A) that extends through the insulation layer, throughout the thickness of the insulation layer, and has a second portion (74B) that extends in the heterostructure. The first portion of the gate region has a first width (Lw) along a second direction (X) transverse to the first direction. The second portion of the gate region has a second width (Lb), along the second direction, that is different from the first width.
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公开(公告)号：EP4224321A1
公开(公告)日：2023-08-09
申请号：EP23151393.8
申请日：2023-01-12
Applicant: STMicroelectronics S.r.l.
Inventor： TORTORA, Gianluca , BARONE, Mario
IPC: G06F11/10
Abstract: A processing system (10a) is described. The processing system (10a) comprises configuration registers (112) and a serial non-volatile memory (12a), wherein each memory slot stores configuration data (CD) and error detection bits (PD). A hardware configuration circuit (108a) sequentially reads the data from the non-volatile memory (12a) and store the data read to respective configuration registers (112) For this purpose, the hardware configuration circuit (108a) receives the bits (DATA) of a current memory slot. Next, the hardware configuration circuit (108a) selectively asserts an error signal (PD_ERR) by comparing the received error detection bits (PD) with calculated error detection bits. When the error signal (PD_ERR) is asserted, the hardware configuration circuit (108a) asserts a further error signal (PD _ERR') indicating whether the data of any of the already read memory slots comprise an error. When the further error signal (PD _ERR') is de-asserted, the hardware configuration circuit (108a) stores the received bits to temporary registers (1098). Otherwise, the hardware configuration circuit (108a) stores predetermined configuration data (DATA') to the temporary registers (1098). Next, the hardware configuration circuit (108a) sequentially stores (1096, 1100) the content of the temporary registers (1098) to respective configuration registers (112). Finally, once having received the data of all memory slots, the hardware configuration circuit (108a) generates a further reset signal (RST2) for resetting at least in part the content of the configuration registers (112) when the further error signal (PD _ERR') is asserted.
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33.发明公开
公开(公告)号：EP4184137A3
公开(公告)日：2023-08-02
申请号：EP22201846.7
申请日：2022-10-17
Applicant: STMicroelectronics S.r.l.
Inventor： BRUNO, Giuseppe , LA MALFA, Antonella , ALESSI, Enrico Rosario , PASSANITI, Fabio
Abstract: A device (130) includes a sensor (200). The sensor includes a thermal infrared sensor or a sensor based on CMOS-SOI-MEMS technology, TMOS. The sensor is capable of performing at least two functions at the same time. The first is remote temperature measurement and the second is presence detection. The sensor passively collects infrared information and a microprocessor (210) coupled to the sensor (200) determines the temperature as well as presence.
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公开(公告)号：EP4215930A1
公开(公告)日：2023-07-26
申请号：EP23151716.0
申请日：2023-01-16
Applicant: STMicroelectronics S.r.l.
Inventor： PASSANITI, Fabio , DE PASCALIS, Daniele , ALESSI, Enrico Rosario
Abstract: Method and device for performing self-tests for electrostatic charge variation sensors. The device comprises a first stimulus electrode (14) configured to transmit a stimulus signal; a first receiving electrode (12) facing the first stimulus electrode (12), the first receiving electrode (12) configured to receive an electrostatic charge variation in a surrounding environment; an electrostatic charge variation sensor (16) coupled to the first receiving electrode (12), the electrostatic charge variation sensor configured to generate a first electrostatic charge variation measurement of the electrostatic charge variation and generate a second electrostatic charge variation measurement of the electrostatic charge variation, the second electrostatic charge variation measurement being generated in response to the stimulus signal being transmitted by the first stimulus electrode; and a processor (18) coupled to the electrostatic charge variation sensor (16), the processor (18) configured to perform a self-test on the electrostatic charge variation sensor using the first electrostatic charge variation measurement and the second electrostatic charge variation measurement, and output a result of the self-test that indicates the electrostatic charge variation sensor has passed or failed the self-test. The self-tests is performed while an electrostatic charge variation sensor is active and without interruption to the application employing the electrostatic charge variation sensor.
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公开(公告)号：EP4187588A9
公开(公告)日：2023-07-26
申请号：EP22206585.6
申请日：2022-11-10
Applicant: STMicroelectronics S.r.l.
Inventor： MAGGI, Luca , DEL SARTO, Marco , GRITTI, Alex , MAIERNA, Amedeo
IPC: H01L23/13 , H01L23/538 , H05K3/46
Abstract: The electronic module (10) has a three-dimensional frame (12), a printed circuit board (15) and a plurality of electronic devices (17). The printed circuit board is fixed to the three-dimensional frame and has a plurality of support portions (37A-37F) which extend transversely to each other in space. The electronic devices (17) are fixed to the printed circuit board and are operatively coupled to each other. The electronic devices are arranged on at least one support portion of the printed circuit board.
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Patent Agency Ranking
公开(公告)号：EP4212983A1
公开(公告)日：2023-07-19
申请号：EP23160273.1
申请日：2015-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： IPPOLITO, Calogero Marco , CHIRICOSTA, Mario
Abstract: A circuit arrangement for the generation of a bandgap voltage reference in CMOS technology, of the type that includes a circuit module (101; 101') for generation of a base-emitter voltage difference comprising at least one pair of PNP bipolar substrate transistors, which comprises a first bipolar substrate transistor (Q1) inserted in a first circuit branch (B1) that identifies a first current path (11) from the supply voltage (Vdd) to ground (GND), and a second bipolar substrate transistor (Q2) inserted in a second circuit branch (B2) that identifies a second current path (12) from the supply voltage (Vdd) to ground (GND), said first bipolar substrate transistor (Q1) and second bipolar substrate transistor (Q2) being connected together via their base electrode, and the second transistor (Q2) having an aspect ratio (N) higher than that of the first transistor (Q), said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") comprising a first CMOS current mirror (102; 402; 402') of an n type, connected between said first branch (B1) and said second branch (B2) and connected via a resistance (R1) for adjustment of the bandgap reference voltage to the second bipolar transistor (Q1), a second CMOS current mirror (103; 103'; 403, 403") of a p type, connected between said first branch (B1) and said second branch (B2), said first current mirror (102; 402; 402') and second current mirror (103; 103'; 403, 403") being connected so that each current mirror repeats the current of the other. Said circuit module (101) for generation of a base-emitter voltage difference comprises just said first bipolar substrate transistor (Q1) inserted in the first circuit branch (B1) and said second bipolar substrate transistor (Q2) inserted in the second circuit branch (B2), the current that flows in said circuit arrangement (100; 200; 200'; 200"; 300; 300'; 300"; 400; 400'; 400") from the supply voltage (Vdd) to ground (GND) flowing only through said first bipolar substrate transistor (Q1) and said second bipolar substrate transistor (Q2).
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公开(公告)号：EP4212894A1
公开(公告)日：2023-07-19
申请号：EP22215074.0
申请日：2022-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： DE CAMPO, Nicola , VENTURELLI, Matteo , BRIVIO, Matteo , FOPPIANI, Mauro
IPC: G01R31/28
Abstract: A system for testing comprising an electronic circuit to be tested (11) and an automatic testing equipment (12),
said electronic circuit (11) to be tested comprising a voltage monitor (110) to be tested comprising a resistive divider (111) receiving at its voltage input an input voltage (VIN) to be monitored and coupled at its output to an input of a comparator (113), a reference input of said comparator (113) being coupled to a reference voltage generator (112) supplying a reference voltage (VREF) setting one or more thresholds of the comparator (113),
wherein said electronic circuit (11) to be tested comprises a Built In Self Test Module (114) coupled to said Automatic Test Equipment (12) and to the inputs and output of said comparator (113), said BIST module (114) being configured upon receiving respective commands from the Automatic Test Equipment (12) to test a reaction time (D LH , D HL ) of the comparator (113) and an offset (VOFS) of the comparator (113),
said Automatic Test Equipment (12) comprising means (125, 126, 127, 128, 129) for performing a respective test of the ratio of the resistor divider (111) by a first voltage measurement (128) of a voltage between an input of the divider (111) and the output of the divider (111) and a test of the reference voltage (VREF) provided by the reference threshold generator (112) by a second voltage measurement (129) of the voltage applied by the reference threshold generator (112) at the reference input node of the comparator (113).-
38.发明公开
公开(公告)号：EP4210056A1
公开(公告)日：2023-07-12
申请号：EP22208619.1
申请日：2022-11-21
Applicant: STMicroelectronics S.r.l.
Inventor： TOMASONI, Alessandro , DISEGNI, Fabio Enrico Carlo , CARISSIMI, Marcella , LO IACONO, Daniele
Abstract: A method for storing information in a coded manner in non-volatile memory cells, providing a group of non-volatile memory cells (11A, 11B, 11C, 11D) of non volatile memory, the memory cell being of the type in which a stored logic state (A, B, C, D), which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current (IcellA, IcellB, IcellC, IcellD) provided by the cell (11A, 11B, 11C, 11D), comprising a determined number (Nc) of non-volatile memory cells which is greater than two, the group of non-volatile memory cells (11A, 11B, 11C, 11D) storing a codeword (CW) formed by the values of said stored states (A, B, C, D) of the cells (11A, 11B, 11C, 11D) of the group taken according to a given order,
wherein
given a set of codewords (CW) obtainable by the stored values (A, B, C, D) in the determined number of non-volatile memory cells (11A, 11B, 11C, 11D) in a group,
storing the information in at least two subsets (SB1, SB2, SB3; SB'1, SB'2) of said set of codewords (CW) comprising each at least a codeword (CW), each codeword (CW) in a same subset having a same Hamming weight,
each codeword (CW) belonging to one subset (SB1, SB2, SB3; SB'1, SB'2) having a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.-
公开(公告)号：EP4210054A1
公开(公告)日：2023-07-12
申请号：EP22211046.2
申请日：2022-12-02
Applicant: STMicroelectronics S.r.l.
Inventor： DISEGNI, Fabio Enrico Carlo , CARISSIMI, Marcella , TOMASONI, Alessandro , LO IACONO, Daniele
Abstract: A sense amplifier architecture (10) for a memory device (1) having a plurality of memory cells (3), wherein groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high ('1') or logic low ('0'), of the memory cells of the group; the sense amplifier architecture (10) has: a plurality of sense amplifier reading branches (15), each sense amplifier reading branch (15) coupled to a respective memory cell (3) and configured to provide an output signal (sCOMP_A), which is indicative of a cell current (I cell ) flowing through the same memory cell (3); a comparison stage (12), to perform a comparison between the cell currents (I cell ) of memory cells (3) of a group; and a logic stage (13), to determine, based on comparison results provided by the comparison stage (12), a read codeword corresponding to the group of memory cells (3). Information may be stored in different subsets (SB1, SB2) of codewords, the sense amplifier architecture (10) in this case having a subset definition circuit (40), to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
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40.发明公开
公开(公告)号：EP4207613A1
公开(公告)日：2023-07-05
申请号：EP22211470.4
申请日：2022-12-05
Applicant: STMicroelectronics S.r.l.
Inventor： BENDOTTI, Valerio , GENNARI SANTORI, Valerio
Abstract: An isolated driver device (10) comprises a first semiconductor die (10a) and a second semiconductor die (10b) galvanically isolated from each other. The second semiconductor die (10b) includes a signal modulator circuit (122) configured to modulate a carrier signal to produce a modulated signal ( FB ) encoding information. A galvanically isolated communication channel (113', 111P', 111N', 110') implemented in the first semiconductor die (10a) and the second semiconductor die (10b) is configured to transmit the modulated signal ( FB ) from the second semiconductor die (10b) to the first semiconductor die (10a). The second semiconductor die (10b) includes: a fault detection circuit (118) configured to detect electrical faults in the second semiconductor die (10b); a logic circuit (114) coupled to the fault detection circuit (118) and configured to assert a modulation bypass signal ( BP ) in response to a fault being detected by the fault detection circuit (118); and modulation masking circuitry (123) configured to force the modulated signal ( FB ) to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal ( BP ) being asserted. The first semiconductor die (10a) includes a respective logic circuit (108) sensitive to the modulated signal ( FB , MOD) and configured to detect a condition where the modulated signal ( FB ) has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal ( FAULT ) in response to the condition being detected.
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