公开(公告)号：EP1459386B1

公开(公告)日：2010-07-14

申请号：EP02783434.0

申请日：2002-11-21

申请人： NXP B.V.

发明人： HIJZEN, Erwin, A. ,  IN 'T ZANDT, Michael, A., A. ,  HUETING, Raymond, J., E.

IPC分类号： H01L29/423 ,  H01L29/872 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/28211 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/872

摘要： In semiconductor devices which include an insulated trench electrode ( 11 ) in a trench ( 20 ), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity ( 23 ) is provided between the bottom ( 25 ) of the trench electrode ( 11 ) and the bottom ( 27 ) of the trench ( 20 ) to reduce the dielectric coupling between the trench electrode ( 11 ) and the body portion at the bottom ( 27 ) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

公开(公告)号：EP2148374A1

公开(公告)日：2010-01-27

申请号：EP08104843.1

申请日：2008-07-23

申请人： University College Cork-National University of Ireland, Cork

发明人： Colinge, Jean-Pierre ,  Afzalian, Aryan

IPC分类号： H01L29/775 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0895 ,  H01L29/125 ,  H01L29/4232 ,  H01L29/7391 ,  H01L29/7613 ,  H01L29/775 ,  H01L29/7831

摘要： The invention provides a new type of transistor comprising a nanowire structure adapted to provide a tunnel barrier such that an applied gate voltage causes a current to oscillate, as the gate voltage is increased, to provide a region of negative transconductance. The device presents oscillations of current as the gate voltage is increased, typically when the cross section of the wire is smaller than 10nm. The sub-threshold slope of the current is larger than 60 mV/decade but can locally reach values smaller than 60 mV/decade in devices with small cross sections. The new transistor has applications in ultra fast switches operating at a very low voltage and in the area of memory devices in the nano-scale.

摘要翻译： 本发明提供了一种新型晶体管，其包括适于提供隧道势垒的纳米线结构，使得所施加的栅极电压随着栅极电压增加而导致电流振荡以提供负跨导区域。 通常当导线的横截面小于10nm时，器件呈现栅极电压升高时的电流振荡。 电流的次阈值斜率大于60 mV /十倍，但在具有小截面的器件中，当地可达到小于60 mV / 10的值。 新型晶体管具有在非常低的电压下工作的超快速开关和纳米级存储器件领域的应用。

公开(公告)号：EP1576651A4

公开(公告)日：2009-09-16

申请号：EP03759404

申请日：2003-09-19

申请人： ADVANCED ANALOGIC TECH INC

发明人： WILLIAMS RICHARD K ,  CORNELL MICHAEL E ,  CHAN WAI TIEN

IPC分类号： H01L21/762 ,  H01L21/8228 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L27/082 ,  H01L21/76 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L27/102 ,  H01L27/105

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

公开(公告)号：EP1901354A1

公开(公告)日：2008-03-19

申请号：EP07010947.5

申请日：2007-06-04

申请人： Interuniversitair Microelektronica Centrum ,  Katholieke Universiteit Leuven (KUL)

发明人： Vandenberghe, William G. ,  Verhulst, Anne S.

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4232 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

摘要： A tunnel Field effect transistor (TFET) is disclosed wherein the gate does not align with the drain, and only overlaps with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device.
In addition to the advantage of an improved switching speed, the proposed structure has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behaviour of the TFET is reduced).

摘要翻译： 公开了隧道场效应晶体管（TFET），其中栅极不与漏极对准，并且仅与至少延伸到源极沟道区域的界面的源重叠，并且可选地与沟道的一部分重叠。 由于较短的栅极，总栅极电容减小，这直接反映在器件的改进的开关速度。 除了改进的开关速度的优点之外，所提出的结构具有处理优点（不需要栅极与漏极的对准），以及性能改善（TFET的双极性行为减少）。

公开(公告)号：EP1033757B1

公开(公告)日：2006-06-21

申请号：EP00300577.4

申请日：2000-01-26

申请人： Hitachi, Ltd. ,  HITACHI HARAMACHI ELECTRONICS CO., LTD.

发明人： Utsumi, Tomoyuki ,  Ozeki, Shoichi ,  Suda, Koichi

IPC分类号： H01L29/423 ,  H01L29/739 ,  H01L29/06

CPC分类号： H01L29/4232 ,  H01L29/42312 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7816

公开(公告)号：EP0899790A3

公开(公告)日：2006-02-08

申请号：EP98115414.9

申请日：1998-08-14

申请人： Infineon Technologies AG

发明人： Goebel, Bernd ,  Bertagnolli, Emmerich ,  Klose, Helmut

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10841 ,  H01L21/76237 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4232 ,  H01L29/4238

摘要： An einer von zwei sich gegenüberliegenden Flanken einer Halbleiterstruktur, die ein Source/Drain-Gebiet (S/D1a) und ein darunter angeordnetes Kanalgebiet (Kaa) eines vertikalen Auswahltransistors umfaßt und die zwischen Gräben angeordnet sein kann, ist in einer Höhe des Kanalgebiets (Kaa) ein Element (Ca) angeordnet, das die Ausbildung eines Kanals verhindert. An beide Flanken grenzen das Source/Drain-Gebiet sowie je eine Wortleitung (Wla) an. Für folded Bitleitungen (Bla) können in den Graben (G2a) jeweils zwei Wortleitungen (Wla) gebildet werden. Die Elemente von entlang eines der Gräben (G2a) benachbarten Halbleiterstrukturen sind dann alternierend an eine Flanke des Grabens (G2a) und an eine Flanke eines benachbarten der Gräben (G2a) angeordnet. Ein Speicherkondensator kann oberhalb eines Substrats (1a) angeordnet oder im Substrat (1a) vergraben sein. Die Verbindung des Auswahltransistors mit einer Bitleitung (Bla) kann auf vielfältige Art erfolgen.

公开(公告)号：EP1615231A1

公开(公告)日：2006-01-11

申请号：EP05013507.8

申请日：2005-06-22

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Yeh, Chih-Chieh

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A multiple-gate memory cell comprises a semiconductor body and a plurality of gates arranged in series on the semiconductor body. A charge storage structure on the semiconductor body includes charge trapping locations beneath gates in the plurality of gates. Circuitry to conduct source and drain bias voltages to the semiconductor body near a first gate and a last gate in the series, and circuitry to conduct gate bias voltages to the plurality of gates are included. The multiple-gate memory cell includes a continuous, multiple-gate channel region beneath the plurality of gates in the series, with charge storage locations between some or all of the gates.

摘要翻译： 一种多栅存储单元包括一半导体本体和串联布置在半导体本体上栅极的多元性。 在半导体主体上的电荷存储结构包括在门的多个栅极之下的电荷俘获位置。 电路进行源极和漏极的偏置电压到S

公开(公告)号：EP1476900A2

公开(公告)日：2004-11-17

申请号：EP02794296.0

申请日：2002-12-18

申请人： Freescale Semiconductor, Inc.

发明人： PASSLACK, Matthias, ,  MEDENDORP, Nicholas, William, Jr.

IPC分类号： H01L21/316

CPC分类号： H01L29/513 ,  C23C14/08 ,  C30B23/02 ,  C30B29/16 ,  H01L21/02112 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02269 ,  H01L21/28194 ,  H01L21/28264 ,  H01L21/31604 ,  H01L21/31666 ,  H01L29/4232 ,  H01L29/511 ,  H01L29/517

摘要： A compound semiconductor structure comprises a first layer (8) of gallium oxide located on a supporting semiconductor structure (7) to form an interface therewith. A second layer (9) of a Ga-Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor (430), a heterojunction bipolar transistor (310), or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga-Gd-oxide. The Ga2O3 layer is used to form a high quality interface with the GaAs-based supporting semiconductor structure while the Ga-Gd-oxide provides a low oxide leakage current density.

公开(公告)号：EP1009035B1

公开(公告)日：2004-07-21

申请号：EP97937855.1

申请日：1997-08-29

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA ,  Ryoden Semiconductor System Engineering Corporation

发明人： Narazaki, Atsushi, Fukuryo Semiconductor Eng. Crp. ,  Souno, Hidetoshi, Ryoden Semicond. Sys. Eng. Corp. ,  Yamashita, Yasunori, Mitsubishi Denki K. K.

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

摘要： The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same, and more particularly to an improvement for enhancing a gate breakdown voltage. In order to achieve the object, gate wirings (9), (10) and (13) are provided to keep away from an upper end (UE) of an edge of a gate trench (6) along its longitudinal direction. More specifically, the gate wiring (9) coupled integrally with an upper surface of a gate electrode (7) is formed apart from the upper end (UE) and the gate wiring (10) is formed on an insulating film (4) also apart from the upper end (UE). The two gate wirings (9) and (10) are connected to each other through the gate wiring (13) formed on a BPSG layer (11). Moreover, an upper face of the gate electrode (7) is positioned on the same level as an upper main surface of a semiconductor substrate (90) or therebelow in the vicinity of the upper end (UE). Consequently, a concentration of an electric field generated in insulating films (8) and (17) covering the upper end (UE) can be relieved or eliminated.

公开(公告)号：EP1186019A4

公开(公告)日：2004-05-26

申请号：EP00932771

申请日：2000-05-24

申请人： WILLIAMS RICHARD K ,  GRABOWSKI WAYNE

发明人： GRABOWSKI WAYNE B ,  WILLIAMS RICHARD K

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/42368 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/8083

摘要： A process of manufacturing a trench gate semiconductor device comprises providing a semiconductor material (600,602); placing the semiconductor material in a reaction chamber; forming a trench (606) at a surface of the semiconductor material; growing an oxide lining (608) on the sidewalls and floor of the trench; depositing a polysilicon layer (610) in the trench; etching the polysilicon layer such that a portion (612) thereof remains near a bottom of the trench; etching a portion of the oxide lining from the sidewalls of the trench, leaving a remaining portion of the oxide lining; performing an anisotropic silicon etch to depress the surface of the portion of the polysilicon layer below the surface of the remaining portion of the oxide lining; heating the semiconductor material to form a first oxide layer (618) on the surface of the portion of the polysilicon layer and a second oxide layer (616) on the sidewalls of the trench; removing the first oxide layer; and depositing a polysilicon layer (619) in the trench to form a gate electrode.