利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

164 条记录 (耗时 0.012 秒)

    Method of forming a bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
    34.
    发明公开
    Method of forming a bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy 失效
    具有自对准发射体的双极晶体管及其选择性和非选择性外延形成的方法

    公开(公告)号：EP0350610A3

    公开(公告)日：1990-08-08

    申请号：EP89109885.7

    申请日：1989-06-01

    申请人： International Business Machines Corporation

    发明人： Burghartz, Joachim N. ,  Ginsberg, Barry J. ,  Mader, Siegfried R.

    IPC分类号： H01L21/331 ,  H01L21/20 ,  H01L29/73

    CPC分类号： H01L29/66287 ,  H01L29/7325 ,  Y10S148/011

    摘要： Bipolar transistors having self-aligned emitter-base regions and a method of forming such transistors using selective and non-selective epitaxy are disclosed. A substrate (12) of semiconductor material of a first conductivity type, a portion of which forms a collector region is provided. A first layer (18) of semiconductor material of a second conductivity type is deposited on said substrate, a portion of which forms an intrinsic base region. Over a portion of said first layer (18) an element (30) of insulating material is formed. Said intrinsic base region is formed below said element (30) and the remainder of said first layer forms an extrinsic base region. A second layer (32) of semicon­ductor material of said second conductivity type is deposited on said first layer (18). A portion of said second layer laterally overgrows onto a portion of an upper surface (33) of said element (30) defining an aperture (29) and leaving an exposed region (31) on the upper surface (33). The second layer (32) forms a portion of the extrinsic base region. On said second layer (32) a layer (42) of insulating material is formed which narrows said aperture (29) and said exposed region (31) of said element (30). Said nar­rowed exposed region (31) of said element (30) is removed to expose a portion (50) of said first layer (21) below said aperture (29) and an emitter region (54) of said first conductivity type is formed in said first layer (21) through said aperture (44).

    Self-aligned bipolar fabrication process
    35.
    发明公开
    Self-aligned bipolar fabrication process 失效
    Selbstausrichtendes Herstellungsverfahrenfürbipolare Halbleiterbauelemente。

    公开(公告)号：EP0260060A1

    公开(公告)日：1988-03-16

    申请号：EP87307756.4

    申请日：1987-09-02

    申请人： BRITISH TELECOMMUNICATIONS public limited company

    发明人： Welbourn, Anthony David ,  Heslop, Christopher John Hedley

    IPC分类号： H01L21/285 ,  H01L21/00 ,  H01L29/72

    CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/2257 ,  H01L21/76205 ,  H01L21/76216 ,  H01L29/7325 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/124

    摘要： Regions of the substrate which are to be the collector sinker and the active area of a bipolar transistor are isolated by forming a trench about them and filling it with a dielectric. The dielectric can be oxide formed in a LOCOS process. A dielectric body, which may be nitride, is formed on part of the active area, and base contacts implanted using it as a mask. Polysilicon is deposited over the whole and then cut to form future metallisation-to-base contacts. The dielectric body is removed and the base implanted through the resulting aperture. Oxide spacers are formed on the sidewall of the aperture and polysilicon deposited. The polysilicon is doped and used to produce the emitter by driving the dopant into the substrate between the oxide spacers.

    摘要翻译： 作为集电极沉降片的衬底的区域和双极晶体管的有源区域通过在其周围形成沟槽并用电介质填充来隔离。 电介质可以在LOCOS工艺中形成氧化物。 可以在有源区域的一部分上形成可以是氮化物的电介质体，并且使用其作为掩模将基底接触植入。 多晶硅沉积在整体上，然后切割以形成未来的金属化到基底的接触。 去除电介质体并通过所得到的孔注入基底。 氧化物间隔物形成在孔的侧壁和沉积的多晶硅上。 多晶硅被掺杂并用于通过将掺杂剂驱动到氧化物间隔物之间​​的衬底中来产生发射极。

    Semiconductor device
    37.
    发明公开
    Semiconductor device 失效
    半导体器件

    公开(公告)号：EP0118102A3

    公开(公告)日：1987-09-30

    申请号：EP84102143

    申请日：1984-02-29

    申请人： HITACHI, LTD.

    发明人： Nakazato, Kazuo ,  Nakamura, Tohru ,  Miyazaki, Takao ,  Natsuaki, Nobuyoshi ,  Ogirima, Masahiko ,  Nagata, Minoru

    IPC分类号： H01L21/285 ,  H01L29/72 ,  H01L27/06

    CPC分类号： H01L29/66272 ,  H01L21/8222 ,  H01L29/72 ,  H01L29/7325

    摘要： The invention deals with a semiconductor device which comprises a semiconductor substrate (11) of a first conductivity type, a semiconductor region (14, 15) formed on said substrate, and a first insulation film (120, 77) provided between said semiconductor region and said semiconductor substrate, wherein said semiconductor substrate is isolated by said insulation film from a polycrystalline silicon layer (79, 121) formed in the periphery of said semiconductor region (14, 15) thereby to reduce the parasitic capacitance, and wherein said insulation film (79, 121) is stretched and arranged on the lower side of said semiconductor region.

    摘要翻译： 本发明涉及一种半导体器件，其包括第一导电类型的半导体衬底（11），形成在所述衬底上的半导体区域（14,15）以及设置在所述半导体区域和第一绝缘膜之间的第一绝缘膜（120,77） 所述半导体衬底，其中所述半导体衬底被所述绝缘膜与形成在所述半导体区域（14,15）周围的多晶硅层（79,121）隔离，从而减小寄生电容，并且其中所述绝缘膜（ 79,121）被拉伸并布置在所述半导体区域的下侧。

    Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
    39.
    发明公开
    Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure 失效
    无外延生长和结构结构形成亚基双极晶体管的方法

    公开(公告)号：EP0078725A3

    公开(公告)日：1987-01-21

    申请号：EP82401917

    申请日：1982-10-19

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Ko, Wen-Chuang

    IPC分类号： H01L21/76 ,  H01L29/72

    CPC分类号： H01L29/7325 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

    摘要： A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.4 microns, thereby substantially reducing the lateral oxidation of the semiconductor silicon islands and making possible devices of extremely small size, typically around 16-18 square microns. During the implantation of channel stop regions between the islands of semiconductor material a thin oxide layer is used to screen the underlying silicon from forming oxidation-induced stacking faults by the subsequent high dose field implantation and oxidation. A nitrogen anneal following this implantation and prior to forming the field oxide further reduces the frequency of stacking faults.