公开(公告)号：EP1301982A2

公开(公告)日：2003-04-16

申请号：EP01928713.5

申请日：2001-04-20

申请人： ATMEL CORPORATION

发明人： PATHAK, Saroj ,  PAYNE, James, E. ,  KUO, Harry, H.

IPC分类号： H02M1/00

CPC分类号： G05F1/465

摘要： A voltage regulator circuit (11) that receives an input signal (450) and provides an output signal (600) that is clamped at a specified voltage desired for an internal circuit. The disclosed voltage regulator circuit includes a plurality of subcircuits including a voltage tracking subcircuit (500) in which the output voltage tracks the input voltage with no voltage drop when the input voltage starts to rise from zero volts. In the input voltage increases to a desired voltage level for the internal circuit, the voltage tracking subcircuit (500) clamps the output voltage to remain at that voltage. If the input voltage further increases to a higher voltage, the voltage tracking subcircuit (500) is disabled and one of a plurality of voltage maintaining subcircuits (550, 560, 570) takes control so that the output voltage remains at the desired voltage for the internal circuit.

公开(公告)号：EP1295430A2

公开(公告)日：2003-03-26

申请号：EP01937795.1

申请日：2001-05-30

申请人： ATMEL CORPORATION

发明人： MAALEJ, Khaled ,  HAMMAN, Emmanuel ,  DEMOL, Amaury ,  LEVY, Yannick

IPC分类号： H04L1/20

CPC分类号： H04L27/3809 ,  H04L1/0057 ,  H04L1/0071 ,  H04L1/20 ,  H04L7/0029 ,  H04L27/3827 ,  H04L27/3872 ,  H04L2027/0032 ,  H04L2027/0036 ,  H04L2027/0038 ,  H04L2027/0055 ,  H04L2027/0057 ,  H04L2027/0071 ,  H04L2027/0081

摘要： A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit (70) that allows for high bit error rate measurements. The dual bit error rate estimator circuit (70) uses information pertaining to the number of corrected bytes from a forward error correction decoder (60) and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter (62) and the FEC decoder (60) are able to output valid data. A comparison (710) between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.

公开(公告)号：EP1163598B1

公开(公告)日：2003-03-19

申请号：EP99964203.6

申请日：1999-12-09

申请人： ATMEL CORPORATION

发明人： AULAS, Maxence

IPC分类号： G06F13/42

CPC分类号： G06F13/4243

摘要： The present invention deals with the control of a data bus (120) by a microcontroller (110), taking into account the fact that memory output drivers require a finite amount of time to electrically release the bus after an output operation. Each memory (130, 132) has an associated wait state number for selectively placing the microcontroller (110) in a wait state of variable length subsequent to a read operation and prior to the next I/O operation.

公开(公告)号：EP1279193A2

公开(公告)日：2003-01-29

申请号：EP01923160.4

申请日：2001-04-04

申请人： ATMEL CORPORATION

发明人： LAM, Ken, M.

IPC分类号： H01L21/56

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/4985 ,  H01L24/02 ,  H01L24/06 ,  H01L24/11 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps (30), or conductive adhesive, is deposited on the metallized wirebond pads (23) on the top surface of a silicon wafer (21). An underfill-flux material (27) is deposited over the wafer (21) and the solder bumps (30). A pre-fabricated interposer substrate (31), made of a metal circuitry (34) and a dielectric base (32), has a plurality of metallized through-holes (38) which are aligned with the solder bumps (30). The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer (34) and the circuitry on the wafer. Solder balls (50) are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

公开(公告)号：EP1212838B1

公开(公告)日：2003-01-29

申请号：EP00944647.7

申请日：2000-06-12

申请人： ATMEL CORPORATION

发明人： MORIN, Marc, A.

IPC分类号： H03M3/02 ,  H03D7/16

CPC分类号： H03D3/006 ,  H03D3/008 ,  H03M3/40 ,  H03M3/41

摘要： A delta-sigma modulator (325) having a downconverter mixer circuit (30) in the forward path of the modulator circuit and an upconverter mixer (38) in the feedback path of the modulator. The modulator (325) consists of a loop filter having two components, a bandpass filter (28) before the downconverter (30) and a low-pass filter (32, 33) after the down-converter. The mixer circuits can be implemented as single-sideband rejection mixers with in-phase and quadrature paths. In such a modulator, the loop filter component after the quadrature mixer include two low-pass filters (32, 33), one for the in-phase forward path and another for the quadrature forward path. The feedback also has two paths, which are recombined in the quadrature upconverter (38) located prior to the DAC (50) which produces a real, analog signal (23) to be fed back to the input. Multiple arrangements of this type of modulator can be implemented, including arrangements having multiple intermediate feedback paths to both the baseband low-pass filter and the bandpass loop filter sections.

公开(公告)号：EP1238430A2

公开(公告)日：2002-09-11

申请号：EP00986833.2

申请日：2000-10-23

申请人： ATMEL CORPORATION

发明人： KOVATS, Julius, A. ,  LAM, Ken, M.

IPC分类号： H01L25/065

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A dual-die integrated circuit package (10) having two integrated circuit chips (14, 16) 'flip chip' attached to each other and with one of the chips (14) being aligned at a specified angle in relation to the other chip (16) to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip. Also, being able to use two chips that are identically constructed from a wafer fabrication standpoint provides the advantage of requiring only one IC design process.

公开(公告)号：EP1224481A1

公开(公告)日：2002-07-24

申请号：EP00967398.9

申请日：2000-08-14

申请人： ATMEL CORPORATION

发明人： DHALIWAL, Surinderjit, S.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/31712 ,  G01R31/31715 ,  G01R31/318572

摘要： A circuit for parametric testing of I/O's including bidirectionals includes logic (100) which ties the I/O's into a single test chain. A pulse is applied moved down the chain to test the switching levels of the input buffers (132, 134, 142, 146) and the output buffers (136, 138, 144, 148). The circuit features the ability to program the bidirectionals (192-194, 196-198) as either inputs (test mode 1) or outputs (test mode 2) and so allows for its input and output buffers to be tested. The test mode can be selected simply by writing to an externally accessed data register.

公开(公告)号：EP0764330B1

公开(公告)日：2002-05-15

申请号：EP96907103.4

申请日：1996-02-22

申请人： ATMEL CORPORATION

发明人： LAMBRACHE, Emil ,  SMARANDOIU, George

IPC分类号： G11C14/00 ,  G11C7/00 ,  G11C16/10

CPC分类号： G06F11/1068 ,  G06F11/1008 ,  G06F12/0893 ,  G06F2212/2022 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3431

摘要： A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache (83) used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages (32) with each memory page further divided into sub-page sectors (59-62), and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit (73) used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.

公开(公告)号：EP1201066A1

公开(公告)日：2002-05-02

申请号：EP01909286.5

申请日：2001-02-15

申请人： ATMEL CORPORATION

发明人： MAALEJ, Khaled ,  HAMMAN, Emmanuel ,  DEMOL, Amaury ,  LEVY, Yannick

IPC分类号： H04L27/38

CPC分类号： H04L27/3809 ,  H04L1/0057 ,  H04L1/0071 ,  H04L7/0029 ,  H04L27/3827 ,  H04L27/3872 ,  H04L2027/0032 ,  H04L2027/0036 ,  H04L2027/0038 ,  H04L2027/0055 ,  H04L2027/0057 ,  H04L2027/0071 ,  H04L2027/0081

摘要： A QAM demodulator having a carrier recovery circuit (50) that includes a phase estimation circuit (506) and an additive noise estimation circuit (507) which produces an estimation of the residual phase noise (518) and additive noise (519) viewed by the QAM demodulator. The phase noise estimation (518) is based on the least mean square error (512) between the QAM symbol (509) decided by a symbol decision circuit (508) and the received QAM symbol (504). The additive noise estimation is based on the same error as in the phase noise estimation (518), except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation (519) is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

公开(公告)号：EP1189235A1

公开(公告)日：2002-03-20

申请号：EP01124283.1

申请日：1996-07-19

申请人： ATMEL CORPORATION

发明人： Jazayeri, Mehdi ,  Hui, Edward S. ,  Korsh, George J.

IPC分类号： G11C7/10 ,  G11C16/26 ,  H03K17/16 ,  H03K19/003

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/26

摘要： A low voltage EPROM which increases its reading speed by charging a word line to a voltage higher than V cc during a read operation. Two voltage pumps, which alternatively place charge on a word line, receive control signals of opposite phase from a temperature insensitive oscillator. The voltage from the two voltage pumps passes through a zero threshold voltage ntype pass device to a word line. The zero threshold voltage n-type pass device receives its control signal from a third voltage pump. In order to make the low voltage EPROM compatible with standard 5V programmers, each output driving circuit consists of a large output driver (55) used under low voltage V cc conditions and a smaller output driver (57) used under standard 5V V cc conditions.

摘要翻译： 一种低电压EPROM，其通过在读取操作期间将字线充电至高于Vcc的电压来增加其读取速度。 两个电压泵可替代地在字线上放置电荷，从温度不敏感的振荡器接收相反相位的控制信号。 来自两个电压泵的电压通过零阈值电压n型通过装置到字线。 零阈值电压n型通过装置从第三电压泵接收其控制信号。 为了使低压EPROM与标准5V编程器兼容，每个输出驱动电路由在低电压Vcc条件下使用的大输出驱动器（55）和在标准5V Vcc条件下使用的较小输出驱动器（57）组成。