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    REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY IN NARROW WIDTH PMOS USING F2 IMPLANTATION
    42.
    发明授权
    REDUCTION OF NEGATIVE BIAS TEMPERATURE INSTABILITY IN NARROW WIDTH PMOS USING F2 IMPLANTATION 有权
    减小负VORTEMPERATURINSTABILITÄTAT PMOS宽度窄使用F2注入

    公开(公告)号：EP1470582B1

    公开(公告)日：2010-06-16

    申请号：EP03734669.9

    申请日：2003-01-14

    申请人： Infineon Technologies AG

    发明人： LIN, Chuan

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76237 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823481 ,  H01L29/1033

    摘要： In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of F2 side wall implantation, comprising:a) forming a shallow trench isolation (STI) region in a substrate;b) forming a gate on a gate oxide in the substrate;c) forming a liner layer in said shallow trench isolation region and subjecting the liner layer to oxidation to form a STI liner oxidation layer;d) implanting F2 into side walls of the STI liner oxidation layer at a large tilted angle in sufficient amounts to affect reduction of negative bias temperature instability after a high density plasma fill of the STI F2 implanted liner oxidation layer; ande) filling the STI F2 implanted structure from step d) with a high density plasma (HDP) fill to affect reduction of negative bias temperature instability.

    C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD
    47.
    发明授权
    C IMPLANTS FOR IMPROVED SIGE BIPOLAR TRANSISTORS YIELD 有权
    用于改进的双晶体晶体管产量的C植入物

    公开(公告)号：EP1396018B1

    公开(公告)日：2009-08-12

    申请号：EP02754741.3

    申请日：2002-06-04

    申请人： International Business Machines

    发明人： COOLBAUGH, Douglas, D. ,  SCHONENBERG, Kathryn, T.

    IPC分类号： H01L21/331 ,  H01L21/265

    CPC分类号： H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

    摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon C, into at one of the following regions of the device: the collector region (16), the sub-collector region (14), the extrinsic base regions (29), and the collector-base junction region (27). In a preferred embodiment each of the aforesaid regions include C implants.

    摘要翻译： 提供了一种改善SiGe双极性产率以及制造SiGe异质结双极性晶体管的方法。 本发明的方法包括将碳C离子注入到器件的以下区域之一中：集电极区域（16），子集电极区域（14），非本征基极区域（29）和集电极基极 结区域（27）。 在一个优选实施例中，每个上述区域包括C植入物。

    NITROGEN BASED IMPLANTS FOR DEFECT REDUCTION IN STRAINED SILICON
    48.
    发明公开
    NITROGEN BASED IMPLANTS FOR DEFECT REDUCTION IN STRAINED SILICON 有权
    STICKSTOFFBASIERTE IMPLANTUR ZUR FEHLERVERRINGERUNG在VERSPANNTEM SILIIUM

    公开(公告)号：EP1955372A4

    公开(公告)日：2009-07-22

    申请号：EP06839704

    申请日：2006-11-03

    申请人： TEXAS INSTRUMENTS INC

    发明人： CHAKRAVARTHI SRINIVASAN ,  CHIDAMBARAM P R ,  KHAMANKAR RAJESH ,  BU HAOWEN ,  GRIDER DOUGLAS T

    IPC分类号： H01L21/31 ,  H01L21/265 ,  H01L23/58 ,  H01L29/06 ,  H01L29/40

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

    摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或改善。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强了晶体管内的载流子的迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时还允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间可以通过将氮添加作为源/漏扩展区形成和/或源极/漏极区形成的一部分而容易地并入氮。 衬底的增强的屈服强度由于应变诱导层而减轻了晶体管的塑性变形。