Abstract:
The invention relates to a circuit for processing an analog signal presenting a time sequence of discrete signal levels. Each discrete signal level is situated in a time interval and represents an information-bearing segment of said interval while the remainder of the time interval is a non-information-bearing segment. The circuit comprises a transistor (10) configured as an emitter-follower or source-follower circuit, a high emitter or source resistance or, in place of same, a high-resistance constant current source (20) and a device (14) for applying a supply voltage, as well as a switch (24) which is connected between the emitter and a reference potential (26) and serves to prevent a current from flowing via the resistance or high-resistance voltage source (20) in case of a charge reversal of an output capacity (22) of the circuit in one direction, whereas in case of a charge reversal in the other direction the dynamic current boosting effect of the transistor (10) is utilized. This results in a rapid emitter-follower or source-follower circuit which can be used notably as output stage for image sensors.
Abstract:
A dual band RF tuning circuit (1) has a first impedance element (4) and a second impedance element (5) between an RF input port (2) and an RF output port (3). Tuning is provided by the impedance elements (4,5) to a first RF signal and a switching transistor (9) is connected to the second impedance element (5) to short the second impedance element (5) for tuning to a second RF signal by the first impedance element (4) alone.
Abstract:
A line receiver (100) comprising a switched capacitor circuit (102) and a buffer (108) is described. The buffer (108) may be configured to receive, through the switched capacitor circuit (102), an analog signal. In response, the buffer (102) may provide an output signal to a load (110), such as an analog-to-digital converter. The switched capacitor circuit (102) may be controlled by a control circuitry (112), and may charge at least one capacitive element (106) to a desired reference voltage. The reference voltage may be selected so as to bias the buffer (108) with a desired DC current, and consequently, to provide a desired degree of linearity. The line receiver (100) may further comprise a bias circuit (300) configured to generate the reference voltage needed to bias the buffer (108) with the desired DC current.
Abstract:
Systems are provided for RF high power generation. An arrangement includes an RF power combiner, at least one RF power amplifier, a switch, a control unit, and a transmission line. The RF power combiner has at least one RF input and at least one RF output. The RF power amplifier is electrically connected to the RF input via the transmission line. The switch is included in the transmission line. The switch is configured to control, by a switching action, transmission of a RF signal from the RF power amplifier to the RF input via the transmission line. The control unit is electrically connected to the switch. The control unit is configured to control the switching action of the switch. The control unit is electrically connected to the switch via the same transmission line.
Abstract:
Arrangement and method for RF high power generation able to compensate a power amplifier module with failure The present invention relates to an arrangement (1) and method for RF high power generation comprising at least one power combiner (2) with RF inputs (3) and at least one RF output (4), and at least two power amplifier modules (5) electrically connected to respectively an input (3) by at least one transmission line (6). At least one RF switch (7) is comprised by the at least one transmission line with a complex load (8) electrically connected to the at least one RF switch (7).
Abstract:
A method of operating an amplifier output of an amplifier as a signal switch, the method including coupling a gate of a switch transistor (102) of the amplifier to a switch signal line, coupling a gate of an amplifier transistor (101) of the amplifier to a gate signal line, and controlling impedance of the amplifier by manipulating gate bias voltages of the transistors (101, 102) via the signal lines.
Abstract:
The present disclosure relates to a radio frequency (RF) communications system, which may include any or all of RF modulation and control circuitry, RF power amplifier (PA) circuitry, a direct current (DC)-DC converter, transceiver circuitry, and front-end aggregation circuitry. Embodiments of the RF communications system may relate to reducing cost, reducing size, reducing complexity, increasing efficiency, increasing performance, the like, or any combination thereof.
Abstract:
A power amplifier comprises a series stack of power amplifier devices, connected in parallel to the amplifier input for receiving an RF input signal, and having output terminals being connected in series to the amplifier output. An intermediate coupling capacitor is connected between each adjacent pair of power amplifier devices in the series stack of power amplifier devices for DC isolation of said power amplifier devices. This reduces the required DC supply voltage, as well as allowing shorting of individual power amplifier devices in response to variation in the DC supply voltage.
Abstract:
An amplifier (100, 300) comprises a main amplification stage (40) and an auxiliary amplification stage (50). An input of the main amplification stage (40) and an input of the auxiliary amplification stage (50) are coupled to a common node (30), and an output of the main amplification stage (40) is coupled to an output node (20). During activation, before power is supplied to the main amplification stage (40), the output node (30) is coupled to a reference voltage (V REF ). A quiescent voltage is then established at the common node (30) by coupling power to the auxiliary amplification stage (50). Only then is power coupled to the main amplification stage (40) and the reference voltage (V REF ) de-coupled from the output node (20).