利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

73 条记录 (耗时 0.014 秒)

    Method for manufacturing non-volatile memory device
    51.
    发明公开
    Method for manufacturing non-volatile memory device 审中-公开
    Herstellungsverfahren von Festwertspeicherbauelement

    公开(公告)号：EP1363324A1

    公开(公告)日：2003-11-19

    申请号：EP02425311.4

    申请日：2002-05-16

    申请人： STMicroelectronics S.r.l.

    发明人： Pividori, Luca ,  Calareso, Carmen

    IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/321

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： A method of manufacturing non-volatile memory devices, comprises the following steps:

    depositing a first layer (3) onto a semiconductor substrate;
    defining and selectively removing said first layer (4) to form a portion (5) of said first layer (4);
    depositing a second layer (7) to a first thickness over the entire memory device;
    forming a screening layer (8) on the second layer (7) to leave uncovered at least a portion (10) of the second layer (7) aligned to the portion (5) of the first layer (3); and
    partly removing the portion (10) of the second layer (7) such that the thickness of the portion (10) of the second layer (7) is made smaller than the first thickness.

    摘要翻译： 制造非易失性存储器件的方法包括以下步骤：将第一层（3）沉积到半导体衬底上; 限定和选择性地去除所述第一层（4）以形成所述第一层（4）的部分（5）; 在整个存储器件上沉积第二层（7）至第一厚度; 在所述第二层（7）上形成屏蔽层（8），以使未覆盖的所述第二层（7）的至少一部分（10）与所述第一层（3）的所述部分（5）对准。 并且部分地去除第二层（7）的部分（10），使得第二层（7）的部分（10）的厚度小于第一厚度。

    NONVOLATILE PMOS TWO TRANSISTOR MEMORY CELL AND ARRAY
    52.
    发明公开
    NONVOLATILE PMOS TWO TRANSISTOR MEMORY CELL AND ARRAY 审中-公开
    不挥发PMOS二晶体管存储单元和阵列

    公开(公告)号：EP0965133A4

    公开(公告)日：2003-02-05

    申请号：EP98950996

    申请日：1998-10-07

    申请人： PROGRAMMABLE MICROELECTRONICS

    发明人： CHANG SHANG-DE TED ,  KOWSHIK VIKRAM ,  YU ANDY TENG-FENG ,  RADJY NADER

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L29/7885

    摘要： A nonvolatile memory array has a plurality of PMOS two transistor (2T) memory cells. Each 2T cell (40) includes a PMOS floating gate transistor (40a) and a PMOS select transistor (40b) and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n-well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

    Single-chip contact-less read-only memory (rom) device and the method for fabricating the device
    53.
    发明公开
    Single-chip contact-less read-only memory (rom) device and the method for fabricating the device 失效
    Einzelchip mit kontaktlosem Festwertspeicherbauelement und das Verfahren zur Herstellung des Bauelements

    公开(公告)号：EP0822598A1

    公开(公告)日：1998-02-04

    申请号：EP97113129.7

    申请日：1997-07-30

    申请人： NEC CORPORATION

    发明人： Hisamune, Yoshiaki

    IPC分类号： H01L27/105 ,  H01L21/8239

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral circuit, for operating the memory cell array, formed on the first surface, and a connecting portion, for electrically connecting the memory cell array to the peripheral circuit, formed on the first surface.

    摘要翻译： 为了获得小的无接触存储器件，存储器件包括具有第一表面和位于比第一表面低的水平的第二表面的半导体芯片，形成在第二表面上的存储单元阵列，外围电路 ，用于操作形成在第一表面上的存储单元阵列和用于将存储单元阵列电连接到形成在第一表面上的外围电路的连接部分。

    PMOS memory cell with hot electron injection programming and tunnelling erasing
    54.
    发明公开
    PMOS memory cell with hot electron injection programming and tunnelling erasing 失效
    通过热电子注入和可擦除通过隧道效应PMOS存储单元编程

    公开(公告)号：EP0778623A3

    公开(公告)日：1997-09-03

    申请号：EP96307350.7

    申请日：1996-10-09

    申请人： Programmable Microelectronics Corporation

    发明人： Chang, Shang-De T.

    IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L21/82

    CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/7885

    摘要： A P-channel MOS memory cell has P+ source (14) and drain (16) regions formed in an N-well (18). A thin tunnel oxide (24) is provided between the well surface and an overlying floating gate (22). In one embodiment, the thin tunnel oxide (24) extends over a substantial portion of the active region (12) of the device. An overlying control gate (26) is insulated from the floating gate (22) by an insulating layer (28). The device is programmed via hot electron injection from the drain end of the channel region (12) to the floating gate (22), without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate (22) to the N-well (18) with the source (14), drain (16), and N-well (18) regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

    Method for etching silicon nitride
    55.
    发明公开
    Method for etching silicon nitride 失效
    蚀刻氮化硅的方法

    公开(公告)号：EP0706206A2

    公开(公告)日：1996-04-10

    申请号：EP95114230.6

    申请日：1995-09-11

    申请人： MOTOROLA, INC.

    发明人： Lin, Jung-Hui ,  Koh, Ai

    IPC分类号： H01L21/311

    CPC分类号： H01L27/11526 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575

    摘要： In accordance with the present invention, a silicon nitride layer (20) in a semiconductor device (10) is anisotropically etched selectively to both silicon dioxide, for example gate oxide layer (16), and to silicon, for example, silicon substrate (12) and polysilicon gate electrode (18). The silicon nitride layer is etched in a plasma etch system using CF₄, O₂, and argon gases. In other applications of the present invention, the etch method is used to remove an ONO dielectric stack and to remove a silicon nitride etch stop layer selectively to both active regions and isolation regions to form contacts or local interconnects across these regions.

    摘要翻译： 根据本发明，半导体器件（10）中的氮化硅层（20）被选择性地蚀刻到二氧化硅（例如栅极氧化物层（16））和硅（例如硅衬底（12） ）和多晶硅栅电极（18）。 利用CF 4，O 2和氩气在等离子体蚀刻系统中蚀刻氮化硅层。 在本发明的其他应用中，使用蚀刻方法去除ONO电介质叠层并选择性去除氮化硅蚀刻停止层到有源区域和隔离区域以在这些区域上形成接触或局部互连。

    Contactless flash EPROM cell using a standard row decoder
    57.
    发明公开
    Contactless flash EPROM cell using a standard row decoder 失效
    使用标准线解码器的无连续闪存EPROM单元

    公开(公告)号：EP0509696A3

    公开(公告)日：1993-02-03

    申请号：EP92303037.3

    申请日：1992-04-07

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Bergemont, Albert M.

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

    摘要： A contactless EPROM cell array in accordance with the present invention comprises an N+ source line formed in the silicon substrate. First and second N+ drain lines are formed in parallel with and spaced-apart from the source line on opposite sides of the source line. First and second field oxide strips are formed in parallel with but spaced-apart from the first and second drain lines, respectively, such that the source line/drain line structure is bounded on both sides by the first and second field oxide strips to separate this structure from adjacent similar source/drain line structures. First and second polysilicon 1 lines overlie the channel regions between the first drain line and the source line and the second drain line and the source line, respectively, and are separated therefrom by a first layer of dielectric material. A plurality of spaced-apart, parallel polysilicon 2 word lines overlie and run perpendicular to the first and second polysilicon 1 lines and are spaced-apart therefrom by a second dielectric material. Thus, the EPROM cells of the array are defined at each crossing of the polysilicon 1 lines and the polysilicon 2 word lines.