公开(公告)号：EP2320565A1

公开(公告)日：2011-05-11

申请号：EP09252562.5

申请日：2009-11-05

申请人： NXP B.V.

发明人： Meijer, Rinze Ida Mechtilidis Peter ,  Elvira Villagra, Luis

IPC分类号： H03K3/356 ,  H03K5/00

CPC分类号： H03K3/356156 ,  H03K2005/00039

摘要： A delay component (312) for connecting to a logic component (302, 304), the delay component (312) having an input pin (314), an output pin (316) and a clock pin (318). The delay component (312) is configured to transmit data from the input pin (314) of the delay component to the output pin (316) of the delay component during a first phase of a clock signal received at the clock pin (318) of the delay component; and not to transmit data from the input pin (314) of the delay component to the output pin (316) of the delay component during a second phase of a clock signal received at the clock pin (318) of the delay component.

摘要翻译： 用于连接到逻辑部件（302,304）的延迟部件（312），所述延迟部件（312）具有输入引脚（314），输出引脚（316）和时钟引脚（318）。 延迟组件（312）被配置为在时钟管脚（318）接收的时钟信号的第一阶段期间将数据从延迟组件的输入引脚（314）发送到延迟组件的输出引脚（316） 延迟组件; 并且在延迟分量的时钟引脚（318）处接收的时钟信号的第二相位期间，不将数据从延迟分量的输入引脚（314）发送到延迟分量的输出引脚（316）。

公开(公告)号：EP2207262A2

公开(公告)日：2010-07-14

申请号：EP09175591.8

申请日：2009-11-10

申请人： AU Optronics Corporation

发明人： Chen, Chung-Chun ,  Yang, Kun-Yen ,  Liao, Wei-Chien

IPC分类号： H03K3/356

CPC分类号： H03K3/356121 ,  H03K3/356156

摘要： A clocked D-type Flip-Flop circuit has a transmission gate to admit an input data and to provide an intermediate output to a clock-controlled inverter based on the clock signals. The clock-controlled inverter is used as a latch for latching the output signal from the transmission gate and releases the latched signal by the same clock signals to an output inverter. The output of the output inverter is the Q terminal of the Flip-Flop circuit. Another output inverter is used to invert the signal from the Q terminal into a complementary output signal. In one of the embodiments of the present invention, another transmission gate is used to condition the complementary output signal.

摘要翻译： 时钟D型触发器电路具有传输门以允许输入数据，并且基于时钟信号向时钟控制的逆变器提供中间输出。 时钟控制逆变器用作锁存来自传输门的输出信号的锁存器，并将相同的时钟信号的锁存信号释放到输出反相器。 输出反相器的输出是触发电路的Q端。 另一个输出反相器用于将来自Q端子的信号转换为互补输出信号。 在本发明的一个实施例中，另一个传输门用于调节互补输出信号。

公开(公告)号：EP2184852A1

公开(公告)日：2010-05-12

申请号：EP09174697.4

申请日：2009-10-30

申请人： FUJITSU LIMITED

发明人： Kanari, Katsunao

IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/356156

摘要： A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan clock input terminal, a logical circuit that performs a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generates an update clock and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holds the data or the scan data provided from the update input terminal when the update clock is provided.

摘要翻译： 锁存电路包括第一锁存器，当从时钟输入端子提供时钟时，存储从数据输入端子提供的数据，并且当从第一扫描时钟提供第一扫描时钟时，存储从扫描数据输入端子提供的扫描数据 输入端子，对从第二扫描时钟输入端子提供的第二扫描时钟和从操作模式输入端子提供的操作模式信号执行逻辑运算的逻辑电路，并产生更新时钟和包括更新的第二锁存器 连接到第一锁存器的输出端子的输入端子和连接到逻辑电路的输出端子的更新时钟输入端子，当提供更新时钟时，第二锁存器保存从更新输入端子提供的数据或扫描数据 。

公开(公告)号：EP1346477B1

公开(公告)日：2009-05-06

申请号：EP01270955.6

申请日：2001-12-05

申请人： NXP B.V.

发明人： GANESAN, Anand

IPC分类号： H03K3/356

CPC分类号： H03K3/356156 ,  H03K3/012 ,  H03K3/0375 ,  H03K3/356121

摘要： A differential cascode structure is configured to propagate a data state to a static latch at each active edge of a clock. A clock generator enables the communication of the data state and its inverse to the latch for a predetermined time interval. In a first embodiment, each cascode structure includes three gates in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse. In an alternative embodiment, each cascode structure includes two gates in series, the gates being controlled by the clock signal and the delayed inversion of the clock signal. In this alternative embodiment, each of these cascode structures is driven directly by the data signal or its inverse. The static latch obviates the need to precharge nodes within the device, thereby minimizing the power consumed by the device. The latch preferably comprises cross-coupled inverters, which, being driven by the differential cascode structure, enhance the switching speed.

公开(公告)号：EP0872956B1

公开(公告)日：2009-03-11

申请号：EP98106814.1

申请日：1998-04-15

申请人： NEC Electronics Corporation

发明人： Ogawa, Tadahiko

IPC分类号： H03K3/356

CPC分类号： H03K3/356156 ,  H03K3/356173 ,  H03K3/35625

公开(公告)号：EP1481476A1

公开(公告)日：2004-12-01

申请号：EP03711226.5

申请日：2003-02-25

申请人： Honeywell International Inc.

发明人： FULKERSON, David, E.

IPC分类号： H03K3/3562

CPC分类号： H03K3/012 ,  H03K3/0372 ,  H03K3/356121 ,  H03K3/356156 ,  H03K3/35625

摘要： A method and apparatus for storing data in a master flip flop, comprising in combination receiving a clock signal having a first and second state, storing a master data state in a master storage device having a master storage input and a master storage output, storing a master complement data state in a master complement storage device having a master complement storage input and a master storage complement output, receiving a data input signal by a transmission gate, receiving a complement data input signal by a complement transmission gate, overriding the master storage complement output with the data input signal when the clock is in the first state, overriding the master storage output with the complement data input signal when the clock is in the first state, disconnecting the master storage complement output from the data input signal when the clock is in the second state, and disconnecting the master storage output from the complement data input signal when the clock is in the second state. The set-up time for the transmission gate is less than two transistor gate delays.

公开(公告)号：EP0929895B1

公开(公告)日：2001-11-28

申请号：EP97910744.8

申请日：1997-09-29

申请人： Advanced Micro Devices, Inc.

发明人： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

摘要： An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP1024594A1

公开(公告)日：2000-08-02

申请号：EP00300376.1

申请日：2000-01-19

申请人： LUCENT TECHNOLOGIES INC.

发明人： Offord, Glen E.

IPC分类号： H03K3/356

CPC分类号： H03K3/35625 ,  H03K3/356156 ,  H03K3/356173

摘要： A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.

摘要翻译： 具有一个或多个级的触发器（例如，主级和在主 - 从从属级触发器，或者一个单级作为一个锁存器），至少一个阶段具有驾驶员耦合在其输入端和 输出到反馈路径以门控反相器具有嵌入预设和/或清晰的逻辑。 通过在反馈路径中嵌入所述预设/清除逻辑，驱动器可以用简单的反相器来实现。 更完了，在预设的和/或透明的功能可以在不无论是设置时间或触发器的时钟到Q的传输时间造成不利影响加入。

公开(公告)号：EP0929895A1

公开(公告)日：1999-07-21

申请号：EP97910744.0

申请日：1997-09-29

申请人： Advanced Micro Devices, Inc.

发明人： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC分类号： G06F12 ,  G11C5 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

摘要： An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP0872956A2

公开(公告)日：1998-10-21

申请号：EP98106814.1

申请日：1998-04-15

申请人： NEC CORPORATION

发明人： Ogawa, Tadahiko

IPC分类号： H03K3/356

CPC分类号： H03K3/356156 ,  H03K3/356173 ,  H03K3/35625

摘要： A latch circuit (X, Y) for eliminating slew current flowing in between power sources during period when clock signal changes. In the latch circuit(X, Y), an input terminal is formed in such a way that dual transfer gates are connected to respective nodes remaining differential signal of bistable circuit which is constituted that one pair of clocked · CMOS inverter is subjected to mesh connection. An output terminal of holding signal of latch circuit is drains of PMOS and NMOS transistors being adjacent to end terminal of power source, which transistors are member of the one pair of clocked · CMOS inverter. Gates of PMOS and NMOS transistors being adjacent to side of output terminal are taken to be input terminal of gate signal of the latch circuit. During period of sampling calculation, since there exists MOS transistor which is connected in series between power sources and which is sure to stand of OFF state, it is capable of cutting transient slew current flowing between power sources (91, 92).

摘要翻译： 一种锁存电路（X，Y），用于在时钟信号变化期间消除在电源之间流动的电流。 在锁存电路（X，Y）中，输入端子形成为使得双传输门连接到构成一对时钟的双稳态电路的各个节点的剩余差分信号。 CMOS逆变器经过网状连接。 锁存电路的保持信号的输出端子是与功率源的端子相邻的PMOS和NMOS晶体管的漏极，该晶体管是一对时钟的晶体管。 CMOS逆变器。 与输出端侧相邻的PMOS和NMOS晶体管的栅极被认为是锁存电路的栅极信号的输入端。 在采样计算期间，由于存在串联连接在电源之间且确定处于OFF状态的MOS晶体管，因此能够切断在电源（91,92）之间流动的瞬态电压电流。