公开(公告)号：EP0929895B1

公开(公告)日：2001-11-28

申请号：EP97910744.8

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP0929895A1

公开(公告)日：1999-07-21

申请号：EP97910744.0

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G06F12 ,  G11C5 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

公开(公告)号：EP0929898B1

公开(公告)日：2001-11-28

申请号：EP97945064.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, Lee ,  HOLST, John, Christian

IPC: G11C8/00

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995 ,  Y02D10/13

Abstract: A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.

公开(公告)号：EP0929896B1

公开(公告)日：2001-11-28

申请号：EP97944574.9

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian

IPC: G11C7/00 ,  G11C17/12

CPC classification number: G11C29/026 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory includes a data bit line and a reference bit line. Word lines in the memory are connected to the bit lines by transistors. The transistors on data bit lines and the reference bit lines are substantially the same size. The capacitances on the data bit lines are substantially the same as the capacitances on the reference bit lines. When the word line is activated, the bit lines express a steady-state voltage that is a function of the resistance of the bit lines. In one example, the data bit lines have a resistance (R) and the reference bit lines have half the resistance (R2). The same current is sourced to the data bit lines and the reference bit lines so that the steady-state voltage of the data bit line differs from the steady-state voltage of the reference bit line by a factor equal to the ratio of the resistances. The resistors (R and R2) perform two functions, the resistors clamp level of the bit lines that are being discharged to stop the displacement current. The data bit lines are sensed differentially with respect to the reference.

Abstract translation: 存储器包括数据位线和参考位线。 存储器中的字线通过晶体管连接到位线。 数据位线和参考位线上的晶体管大小基本相同。 数据位线上的电容基本上与参考位线上的电容相同。 当字线被激活时，位线表示作为位线电阻的函数的稳态电压。 在一个示例中，数据位线具有电阻（R）并且参考位线具有电阻的一半（R2）。 相同的电流源于数据位线和参考位线，使得数据位线的稳态电压与参考位线的稳态电压相差等于电阻比的因子。 电阻（R和R2）执行两个功能，电阻钳位正在放电的位线的电平以停止位移电流。 数据位线相对于参考差分地被感测。

公开(公告)号：EP0929939A1

公开(公告)日：1999-07-21

申请号：EP97945362.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PARTOVI, Hamid ,  HOLST, John, Christian ,  BEN-MEIR, Amos

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.

公开(公告)号：EP0929898A1

公开(公告)日：1999-07-21

申请号：EP97945064.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, Lee ,  HOLST, John, Christian

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995 ,  Y02D10/13

Abstract: A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.

公开(公告)号：EP0929896A1

公开(公告)日：1999-07-21

申请号：EP97944574.0

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory includes a data bit line and a reference bit line. Word lines in the memory are connected to the bit lines by transistors. The transistors on data bit lines and the reference bit lines are substantially the same size. The capacitances on the data bit lines are substantially the same as the capacitances on the reference bit lines. When the word line is activated, the bit lines express a steady-state voltage that is a function of the resistance of the bit lines. In one example, the data bit lines have a resistance (R) and the reference bit lines have half the resistance (R2). The same current is sourced to the data bit lines and the reference bit lines so that the steady-state voltage of the data bit line differs from the steady-state voltage of the reference bit line by a factor equal to the ratio of the resistances. The resistors (R and R2) perform two functions, the resistors clamp level of the bit lines that are being discharged to stop the displacement current. The data bit lines are sensed differentially with respect to the reference.