公开(公告)号：EP2006248A3

公开(公告)日：2012-06-06

申请号：EP08158292.6

申请日：2008-06-13

Applicant: Honeywell International Inc.

Inventor： Eskridge, Mark H. c/o Honeywell Int. Inc.

IPC: B81B7/00

CPC classification number: B81B7/0048 ,  B81B2201/0235 ,  B81B2201/0242 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05001 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: One method of the present invention includes preparing a die (24) with traces and pads as desired for the intended use of the die (24). A MEMS device (22) is mounted to the die (24). The die is then mounted to a substrate of the same material as the die (24). The substrate is then mounted to a package (28). The die (24) and/or the substrate may be flip-chip mounted.

公开(公告)号：EP2455330A2

公开(公告)日：2012-05-23

申请号：EP11190202.9

申请日：2011-11-22

Applicant: Honeywell International, Inc.

Inventor： Horning, Robert D.

IPC: B81B7/02 ,  B81B7/00

CPC classification number: B81B7/02 ,  B81B7/0041 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2207/095 ,  B81B2207/096 ,  B81C2201/019 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Systems and methods for a micro-electromechanical system (MEMS) apparatus are provided. In one embodiment, a system comprises a first double chip that includes a first base layer; a first device layer bonded to the first base layer, the first device layer comprising a first set of MEMS devices; and a first top layer bonded to the first device layer, wherein the first set of MEMS devices is hermetically isolated. The system also comprises a second double chip that includes a second base layer; a second device layer bonded to the second base layer, the second device layer comprising a second set of MEMS devices; and a second top layer bonded to the second device layer, wherein the second set of MEMS devices is hermetically isolated, wherein a first top surface of the first top layer is bonded to a second top surface of the second top layer.

Abstract translation: 提供了一种用于微机电系统（MEMS）装置的系统和方法。 在一个实施例中，系统包括第一双芯片，其包括第一基层; 结合到第一基层的第一器件层，第一器件层包括第一组MEMS器件; 以及结合到第一器件层的第一顶层，其中第一组MEMS器件被气密隔离。 该系统还包括第二双芯片，其包括第二基层; 结合到第二基层的第二器件层，第二器件层包括第二组MEMS器件; 以及结合到所述第二器件层的第二顶层，其中所述第二组MEMS器件是气密隔离的，其中所述第一顶层的第一顶表面接合到所述第二顶层的第二顶表面。

公开(公告)号：EP2447209A1

公开(公告)日：2012-05-02

申请号：EP11182970.1

申请日：2011-09-27

Applicant: Thales

Inventor： Leverrier, Bertrand ,  Lefort, Olivier ,  Boura, André ,  Chaumet, Bernard

IPC: B81B3/00 ,  B81B7/00

CPC classification number: B81B7/0048 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0109 ,  G01C19/5719

Abstract: Le microsystème électromécanique est muni d'au moins deux éléments de fixation disjoints (F1, F2) adaptés pour être fixés sur un support. Un élément de fixation (F1, F2) est lié solidairement à au moins une poutre (P1, P2) déformable en flexion, et deux poutres (P1, P2) liées respectivement à deux éléments de fixation (F1, F2) distincts ont des directions différentes. Une poutre aune longueur L, une épaisseur e, et une hauteur h, telles que les raideurs KL selon les directions de la longueur et de la hauteur Kh soient fortes et la raideur selon la direction de l'épaisseur Ke soit faible.

Abstract translation: 该系统具有适于固定在支撑件即壳体上的不相交的紧固件（F1，F2）。 紧固件中的一个牢固地连接到柔性可变形梁（P1，P2）。 分别连接到紧固件的梁具有不同的方向，其中每个梁具有长度，厚度和高度，使得沿长度和高度方向的刚度强，并且沿着厚度方向的刚度较弱。 梁具有正交方向。 还包括用于固定微机电系统的方法的独立权利要求。

公开(公告)号：EP2202791A2

公开(公告)日：2010-06-30

申请号：EP10160512.9

申请日：2005-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

IPC: H01L23/48 ,  H01L21/762

CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a body (1) and, in the body (1): a semiconductor substrate (2), a semiconductor structural layer (10) and a dielectric layer (12) therebetween. A through interconnection via (30) traverses the body (1) and extends through the dielectric layer (12). The through interconnection via (30) has: a front-side interconnection region (17), including a portion of the structural layer (10) that extends between the dielectric layer (12) and a front face (10a) of the body (1) and is laterally insulated from the remainder of the structural layer (10); a back-side interconnection region (27), including a portion of the substrate (2) that extends between the dielectric layer (12) and a back face (2a) of the body (1) and is laterally insulated from the remainder of the substrate (2) by a back-side insulation trench (29). The back-side insulation trench (29) extends across the entire substrate (2; 102; 202), from the back face (2a) of the body (1) to the dielectric layer (12) the; and a conductive continuity region (8) connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

Abstract translation: 一种半导体器件包括主体（1），并且在主体（1）中：半导体衬底（2），半导体结构层（10）和其间的介电层（12）。 （30）的直通互连穿过主体（1）并延伸穿过介电层（12）。 （30）的贯穿互连具有：正面互连区域（17），其包括在介电层（12）和主体（1）的正面（10a）之间延伸的结构层（10）的一部分 ）并且与结构层（10）的其余部分横向绝缘; 包括在所述介电层（12）和所述主体（1）的背面（2a）之间延伸的所述衬底（2）的一部分的背侧互连区域（27），并且与所述衬底 衬底（2）通过背侧绝缘沟槽（29）。 背面绝缘沟槽（29）从主体（1）的背面（2a）延伸到整个衬底（2; 102; 202）到介电层（12） 以及通过介电层（12）连接前侧互连区域（17）和后侧互连区域（27）的导电连续区域（8）。

公开(公告)号：EP2093184A2

公开(公告)日：2009-08-26

申请号：EP09152338.1

申请日：2009-02-07

Applicant: Honeywell International Inc.

Inventor： Ridley, Jeff A. ,  Higashi, Robert ,  Detry, James F.

IPC: B81B7/00

CPC classification number: B81B7/0087 ,  B81B2201/0242 ,  B81B2201/0278

Abstract: A MEMS device includes a P-N device formed on a silicon pin, which is connected to a silicon sub-assembly, and where the P-N device is formed on a silicon substrate that is used to make the silicon pin before it is embedded into a first glass wafer. In one embodiment, forming the P-N device includes selectively diffusing an impurity into the silicon pin and configuring the P-N device to operate as a temperature sensor.

Abstract translation: MEMS器件包括形成在硅引脚上的PN器件，其连接到硅子组件，并且其中PN器件形成在硅衬底上，所述硅衬底在其被嵌入第一玻璃中之前用于制造硅销 晶圆。 在一个实施例中，形成P-N器件包括选择性地将杂质扩散到硅引脚中并将P-N器件配置为用作温度传感器。

公开(公告)号：EP1096259B1

公开(公告)日：2008-12-03

申请号：EP00122364.3

申请日：2000-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang, Seok-jin ,  Ko, Youn-il ,  Kim, Ho-suk

IPC: G01P15/08 ,  G01C19/56 ,  B81B7/00 ,  G01P1/02 ,  B81C3/00 ,  B81B7/02

CPC classification number: B81C1/0023 ,  B81B2201/0242 ,  B81C2203/0109 ,  B81C2203/019 ,  G01C19/56 ,  G01P1/023 ,  G01P15/0802

公开(公告)号：EP1953815A1

公开(公告)日：2008-08-06

申请号：EP06833257.6

申请日：2006-11-24

Applicant: MATSUSHITA ELECTRIC WORKS, LTD.

Inventor： OKUDO, Takafumi ,  SUZUKI, Yuji ,  TAKEGAWA, Yoshiyuki ,  BABA, Toru ,  GOTOU, Kouji ,  MIYAJIMA, Hisakazu ,  KATAOKA, Kazushi ,  SAIJO, Takashi

IPC: H01L23/02 ,  G01P15/12

CPC classification number: G01P1/023 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/038 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/18 ,  G01P2015/0842

Abstract: A wafer level package structure with a plurality of compact sensors such as acceleration sensors and gyro sensors is provided. This package structure is composed of a semiconductor wafer with plural sensor units, and a pair of package wafers bonded to both surfaces of the semiconductor wafer. Each of the sensor units has a frame having an opening, a movable portion held in the opening to be movable relative to the frame, and a detecting portion for outputting an electric signal according to a positional displacement of the movable portion. Since the semiconductor wafer is bonded to each of the package wafers by a solid-phase direct bonding without diffusion between a surface-activated region formed on the frame and a surface-activated region formed on the package wafer, it is possible to prevent that variations in sensor characteristics occur due to residual stress at the bonding interface.

Abstract translation: 提供如加速度传感器和陀螺仪传感器：与紧凑的传感器的多个晶圆级封装结构。 这种封装结构由具有多个传感器单元的半导体晶片，并接合到所述半导体晶片的两个表面上的一对封装晶片的。 每个传感器单元的具有在开口的框架，在开口保持的可动部可相对于所述框架可移动的，和用于检测输出开始的电信号gemäß可动部的位置偏移的部分。 由于半导体晶片接合到每一个由固相直接结合的封装晶片的未形成所述框架和形成在封装晶片上的表面活化区域上的表面活化区域之间的扩散，所以能够防止那样的变化 在传感器特性的发生是由于在结合界面处的残余应力。

公开(公告)号：EP1788624A1

公开(公告)日：2007-05-23

申请号：EP05425807.4

申请日：2005-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

IPC: H01L23/48

CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body (1) comprising a structural layer (10), a substrate (2), and a dielectric layer (12) set between the structural layer (10) and the substrate (2); insulating a portion of the structural layer (10) to form a front-side interconnection region (17); insulating a portion of the substrate (2) to form a back-side interconnection region (27); and connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

Abstract translation: 在半导体器件中制造通孔的方法包括以下步骤：形成包括结构层（10），基底（2）和设置在结构层（10）之间的介电层（12）的主体（1） ）和基板（2）; 绝缘所述结构层（10）的一部分以形成正面互连区域（17）; 绝缘所述基板（2）的一部分以形成背面互连区域（27）; 并且通过电介质层（12）将前侧互连区域（17）和背面侧互连区域（27）连接起来。

公开(公告)号：EP1725496A1

公开(公告)日：2006-11-29

申请号：EP05721189.8

申请日：2005-03-15

Applicant: MATSUSHITA ELECTRIC WORKS, LTD.

Inventor： GOUDA, Kazuo MATSUSHITA ELECTRIC WORKS, LTD. ,  TSUJI, Koji MATSUSHITA ELECTRIC WORKS, LTD. ,  KIRIHARA, Masao MATSUSHITA ELECTRIC WORKS, LTD. ,  NISHIJIMA, Youichi MATSUSHITA ELECTRIC WORKS, LTD.

IPC: B81C1/00

CPC classification number: B81C1/00142 ,  B81B2201/0242 ,  B81B2203/0136 ,  B81B2203/0353

Abstract: Disclosed is a method of manufacturing a semiconductor device. In this method, a concave portion (7) is formed in one surface in the thickness direction of a primary base plate (1) comprising a semiconductor substrate with a relatively large thickness dimension. Then, through-holes (4a, 4b) are formed by a reactive-ion etching process using as a mask an opening (8) formed in an oxide film (6a) provided on the other surface in the thickness direction of the primary base plate (1). The opening (8) has a narrow width in a region corresponding to the concave portion (7) and a wide width in the remaining region. Thus, respective times necessary for the wide-width through-hole (4a) to penetrate through the primary base plate (1) and necessary for the narrow-width through-hole (4b) to reach a bottom surface of the concave portion (7) can be approximately equalized to complete the common etching process of the wide-width through-hole (4a) and the narrow-width through-hole (4b) approximately simultaneously.

Abstract translation: 公开了一种制造半导体器件的方法。 在该方法中，在包括具有相对较大厚度尺寸的半导体衬底的主基板（1）的厚度方向上的一个表面中形成凹部（7）。 然后，通过反应离子蚀刻工艺形成通孔（4a，4b），该反应离子蚀刻工艺使用形成于设置在主基板的厚度方向上的另一表面上的氧化物膜（6a）中的开口（8） （1）。 开口（8）在与凹部（7）对应的区域具有较窄的宽度，在其余区域具有较宽的宽度。 因此，宽幅通孔4a穿过主基板1并且窄宽度通孔4b到达凹部7的底表面所需的相应时间 ）大致均匀化，几乎同时完成宽幅通孔（4a）和窄幅通孔（4b）的通常的蚀刻处理。

公开(公告)号：EP1675803A2

公开(公告)日：2006-07-05

申请号：EP04821217.9

申请日：2004-10-19

Applicant: Honeywell International Inc.

Inventor： HORNING, Robert, D. ,  RIDLEY, Jeffrey, A.

IPC: B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0242 ,  B81C2203/0118

Abstract: A method for fabricating a MEMS device (300) having a top cap (250) and an upper sense plate is described. The method includes producing (152) a device wafer (230) including an etched substrate (186), etched MEMS device components, and interconnect metal (198, 200), a portion of the interconnect metal being bond pads (132) and adding (154) a metal wraparound layer (232) to a back side (330), edges (320), and a portion of a front side (342) of the device wafer. The method also includes producing (156) an upper wafer including an etched substrate and interconnect metal, bonding (160) the device wafer and the upper wafer, and dicing (164) the bonded upper wafer and device wafer into individual MEMS devices.