公开(公告)号：EP3026706A2

公开(公告)日：2016-06-01

申请号：EP15191735.8

申请日：2015-10-27

申请人： Renesas Electronics Corporation

发明人： MIHARA, Tatsuyoshi

IPC分类号： H01L27/115

CPC分类号： H01L27/11517 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A selection gate electrode is formed over a semiconductor substrate via a first insulation film. Over the opposite side surfaces of the selection gate electrode, second insulation films of sidewall insulation films are formed. Over the semiconductor substrate, a memory gate electrode is formed via a third insulation film having a charge accumulation part. The selection gate electrode and the memory gate electrode are adjacent to each other via the second insulation film and the third insulation film. The second insulation film is not formed under the memory gate electrode. The total thickness of the second insulation film and the third insulation film interposed between the selection gate electrode and the memory gate electrode is larger than the thickness of the third insulation film interposed between the semiconductor substrate and the memory gate electrode.

摘要翻译： 具有非易失性存储器的半导体器件的可靠性和性能得到改善。 选择栅电极经由第一绝缘膜形成在半导体衬底上。 在选择栅电极的相对侧表面上形成侧壁绝缘膜的第二绝缘膜。 在半导体衬底上，经由具有电荷累积部分的第三绝缘膜形成存储器栅电极。 选择栅极电极和存储器栅极电极经由第二绝缘膜和第三绝缘膜彼此相邻。 存储栅电极下方不形成第二绝缘膜。 介于选择栅极电极和存储器栅极电极之间的第二绝缘膜和第三绝缘膜的总厚度大于插入在半导体衬底和存储器栅极电极之间的第三绝缘膜的厚度。

公开(公告)号：EP2988331A1

公开(公告)日：2016-02-24

申请号：EP15188426.9

申请日：2001-08-13

申请人： SanDisk 3D LLC

发明人： LEE, Thomas H. ,  SUBRAMANIAN, Vivek ,  CLEEVES, James M. ,  WALKER, Andrew J. ,  PETTI, Christopher ,  KOUZNETZOV, Igor G. ,  JOHNSON, Mark G. ,  FARMWALD, Paul M. ,  HERNER, Brad

IPC分类号： H01L27/115 ,  G11C16/34 ,  H01L21/822 ,  H01L29/423 ,  H01L29/66 ,  H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L27/12 ,  H01L29/861 ,  H01L27/112 ,  H01L29/16

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。

公开(公告)号：EP2870629A1

公开(公告)日：2015-05-13

申请号：EP13813187.5

申请日：2013-07-03

申请人： Micron Technology, Inc.

发明人： HA, Chang, Wan ,  WOLSTENHOLME, Graham R. ,  THIMMEGOWDA, Deepak

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

公开(公告)号：EP2745321A4

公开(公告)日：2015-04-01

申请号：EP12824323

申请日：2012-08-14

申请人： MICRON TECHNOLOGY INC

发明人： TESSARIOL PAOLO ,  MAURI AURELIO GIANCARLO ,  GODA AKIRA ,  ZHAO YIJIE

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/10

CPC分类号： H01L29/1054 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： Apparatuses, such as memory devices, memory cell strings, and electronic systems, and methods of forming such apparatuses are shown. One such apparatus includes a channel region that has a minority carrier lifetime that is lower at one or more end portions, than in a middle portion. Other apparatuses and methods are also disclosed.

公开(公告)号：EP2308084B1

公开(公告)日：2014-10-08

申请号：EP09794154.6

申请日：2009-07-01

申请人： Kabushiki Kaisha Toshiba

发明人： FUKUZUMI, Yoshiaki ,  TANAKA, Hiroyasu ,  KOMORI, Yosuke ,  ISHIDUKI, Megumi ,  KITO, Masaru ,  AOCHI, Hideaki ,  KATSUMATA, Ryota ,  KIDOH, Masaru

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

公开(公告)号：EP2718973A2

公开(公告)日：2014-04-16

申请号：EP12796567.1

申请日：2012-06-05

申请人： Micron Technology, Inc.

发明人： BANNA, Srinivasa, R. ,  VAN BUSKIRK, Michael, A. ,  THURGATE, Timothy

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

公开(公告)号：EP2652772A2

公开(公告)日：2013-10-23

申请号：EP11848968.1

申请日：2011-12-16

申请人： Spansion LLC

发明人： CHEN, Tung-Sheng ,  FANG, Shenqing

IPC分类号： H01L21/027

CPC分类号： H01L21/302 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

摘要： A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

摘要翻译： 公开了一种双重图案化方法。 在一个实施例中，通过在光致抗蚀剂图案的边缘周围放置间隔图案来开始在多个核心字线的任一侧上形成一对选择栅极字线。 将光致抗蚀剂图案剥离留下间隔图案。 修剪掩模放置在间隔图案的一部分上。 间隔图案的部分被蚀刻掉，不被修剪掩模覆盖。 去除修剪掩模，其中间隔图案的第一剩余部分限定多个核心字线。 放置焊盘掩模，使得焊盘掩模和间隔物图案的第二剩余部分在多个核心字线的任一侧上限定选择栅极字线。 最后，通过使用激光掩模和间隔物图案的第一和第二剩余部分来蚀刻至少一个图案转移层，以将选择栅极字线和多个核心字线蚀刻成多晶硅层。

公开(公告)号：EP2575139A2

公开(公告)日：2013-04-03

申请号：EP12168805.5

申请日：2012-05-22

申请人： eMemory Technology Inc.

发明人： Hsiao, Kai-Yuan ,  Lee, Wen-Yuan ,  Ting, Yun-Jen ,  Liu, Cheng-Jye ,  Sun, Wein-Town

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： G11C16/0466 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0416 ,  H01L27/11565 ,  H01L29/792

摘要： Each memory cell (10) of a plurality of memory cells (130A-130I) of a memory has a well, source (132) and drain (133) regions, a storage layer (135), and a gate (131). The memory cells (130A-130I) are in a matrix. Same column drain regions (133) connect to the same bit line (110A-110C), same row gates (131) connect to the same word line (100A-100C), and same column source regions (132) connect to the same source line (120A-120C). The memory (10) is programmed by applying a first voltage to a word line (100A-100C) electrically connected to a memory cell (130E) of the plurality of memory cells (10), applying a second voltage different from the first voltage by at least a programming threshold to a bit line (110A-110C) electrically connected to the memory cell (130E), applying a third voltage different from the first voltage by at least the programming threshold to a source line (120A-120C) electrically connected to the memory cell (130E), and applying a substrate voltage to the plurality of memory cells (10, 130E).

摘要翻译： 存储器的多个存储单元（130A-130I）的每个存储器单元（10）具有阱，源极（132）和漏极（133）区域，存储层（135）和栅极（131）。 存储单元（130A-130I）是矩阵。 相同的列漏极区（133）连接到相同的位线（110A-110C），相同的行栅极（131）连接到相同的字线（100A-100C），同一列源极区（132）连接到相同的源 线（120A-120C）。 通过向与多个存储单元（10）的存储单元（130E）电连接的字线（100A-100C）施加第一电压来对存储器（10）进行编程，将不同于第一电压的第二电压施加 电连接到存储单元（130E）的位线（110A-110C）的至少编程阈值，将与第一电压不同的至少编程阈值的第三电压施加到电连接的源极线（120A-120C） 到所述存储单元（130E），以及向所述多个存储单元（10,130E）施加衬底电压。

公开(公告)号：EP2264756B1

公开(公告)日：2012-08-29

申请号：EP08739557.0

申请日：2008-03-31

申请人： Fujitsu Semiconductor Limited

发明人： TORII, Satoshi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/02 ,  G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L29/7881

公开(公告)号：EP2253014A4

公开(公告)日：2012-05-23

申请号：EP09719271

申请日：2009-03-12

申请人： MICRON TECHNOLOGY INC

发明人： PEKNY THEODORE

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/0649

摘要： Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second string of serially-coupled second memory cells sharing a single conductive pillar which forms a channel for both strings of serially-coupled memory cells. For example, a first memory cell can have a first control gate on the first side of the conductive pillar and a first charge trap interposed between the first side of the conductive pillar and the first control gate. A second memory cell can have a second control gate on the second side of the conductive pillar and a second charge trap interposed between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other and the first and second control gates can be electrically isolated from each other.

摘要翻译： 公开了存储器阵列和形成存储器阵列的方法。 一个这样的存储器阵列具有串联耦合的第一存储器单元的第一串和共享单个导电柱的第二串串联的第二存储器单元，其形成用于两串串联存储器单元的通道。 例如，第一存储单元可以在导电柱的第一侧上具有第一控制栅极，以及插入在导电柱的第一侧和第一控制栅极之间的第一电荷阱。 第二存储单元可以在导电柱的第二侧上具有第二控制栅极，以及插入在导电柱的第二侧和第二控制栅极之间的第二电荷阱。 第一和第二充电陷阱彼此电隔离，并且第一和第二控制栅极可以彼此电隔离。