公开(公告)号：EP3995788A1

公开(公告)日：2022-05-11

申请号：EP21207025.4

申请日：2021-11-08

Applicant: STMicroelectronics S.r.l.

Inventor： DELLUTRI, Michele Alessio ,  PASSANITI, Fabio ,  ALESSI, Enrico Rosario

IPC: G01F1/64 ,  G01F1/704 ,  G01N27/90

Abstract: A device for measuring (1) the flow of fluid inside a tube (2) moved by a peristaltic pump (3) is provided with: a detection electrode arrangement (6) coupled to the tube (2) to detect an electrostatic charge variation originated by the mechanical action of the peristaltic pump (3) on the tube (2); a signal processing stage (8), electrically coupled to the detection electrode arrangement (6) to generate an electrical charge variation signal (S Q ); and a processing unit (10), coupled to the signal processing stage (8) to receive and process in the frequency domain the electrical charge variation signal (S Q ) to obtain information on the flow of a fluid that flows through the tube (2) based on the analysis of frequency characteristics of the electrical charge variation signal (S Q ).

公开(公告)号：EP3979140A1

公开(公告)日：2022-04-06

申请号：EP21191005.4

申请日：2021-08-12

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： CAPPETTA, Mr. Carmine ,  BOESCH, Mr. Thomas ,  DESOLI, Mr. Giuseppe

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F13/40 ,  G06F12/00 ,  G06F9/50

Abstract: A convolutional accelerator framework or CAF (1100) has a plurality of processing circuits (1190) including one or more convolution accelerators (1192), a reconfigurable hardware buffer (1170) configurable to store data of a variable number of input data channels, and a stream switch (1180) coupled to the plurality of processing circuits (1190, 1192). The reconfigurable hardware buffer (1170) has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch (1180) streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits (1190, 1192) and the reconfigurable hardware buffer (1170) during processing of the execution epoch. The control circuity of the reconfigurable hardware buffer (1170) configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.

公开(公告)号：EP3968372A1

公开(公告)日：2022-03-16

申请号：EP21196140.4

申请日：2021-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： MINOTTI, Agatino

IPC: H01L23/538 ,  H01L23/498

Abstract: Packaged device (57) having a carrying base (30); an accommodation cavity (32) in the carrying base; a semiconductor die (37) in the accommodation cavity (32), the semiconductor die having die pads (39); a protective layer (40), covering the semiconductor die and the carrying base; first vias (43A) in the protective layer, at the die pads (39); and connection terminals (49) of conductive material. The connection terminals have first connection portions (45A) in the first vias (43A), in electrical contact with the die pads (39), and second connection portions (46B, 55), extending on the protective layer (40), along a side surface (57C) of the packaged device.

公开(公告)号：EP3913681A3

公开(公告)日：2022-03-16

申请号：EP21174210.1

申请日：2021-05-17

Applicant: STMicroelectronics S.r.l.

Inventor： FERRARI, Paolo ,  VILLA, Flavio Francesco ,  ZULLINO, Lucia ,  NOMELLINI, Andrea ,  SEGHIZZI, Luca ,  ZANOTTI, Luca ,  SCOLARI, Martina ,  MURARI, Bruno

IPC: H01L27/16 ,  H01L35/22 ,  H01L35/34 ,  H01L31/052

Abstract: A method of fabricating a thermoelectric converter comprises: providing a layer (115; 215) of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements (133a; 237; 330a) of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements (133b; 249; 330b) of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer (115; 215) thickness, from the first surface to the second surface; forming electrically conductive interconnections (143, 413; 257, 413) in correspondence of the first surface and of the second surface of the layer of Silicon-based material (115; 215),, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and forming an input electrical terminal (257') and an output electrical terminal (257") electrically connected to the electrically conductive interconnections, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material comprise Silicon-based materials selected among porous Silicon or polycrystalline SiGe or polycrystalline Silicon.

公开(公告)号：EP3955169A1

公开(公告)日：2022-02-16

申请号：EP21186854.2

申请日：2021-07-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： LA ROSA, Francesco ,  CONTE, Antonino

IPC: G06N3/063 ,  G06F17/16 ,  G11C11/54 ,  G11C11/56

Abstract: The method for convolutional computation (CNVL) comprises programming floating gate transistors (FGT) belonging to non-volatile memory cells (NVM) to multilevel threshold voltages (MLTLVL) according to weight factors (W11-Wnm) of a convolutional matrix operator (MTXOP). The computation comprises performing a multiply and accumulate sequence (MACi) during a sensing operation (SNS) of memory cells (NVMij), the time (T) elapsed for each memory cell to become conductive in response to a voltage ramp control signal (VRMP) providing the value of each product of input values (A1 ... An) by a respective weight factor (Wi1 ... Win), the values of the products being accumulated to corresponding output values (Bi).

公开(公告)号：EP3951403A1

公开(公告)日：2022-02-09

申请号：EP21190136.8

申请日：2021-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： RIZZINI, Francesco ,  VALZASINA, Carlo ,  GATTERE, Gabriele

IPC: G01P15/125 ,  G01P15/08

Abstract: A microelectromechanical sensor device (20) has a detection structure (21) provided with: a substrate (24) having a top surface (24a) extending in a horizontal plane (xy); a mobile structure (22, 26), having an inertial mass (22) suspended above the substrate at a first area (24') of the surface so as to perform at least one inertial movement with respect to the substrate as a function of a quantity to be detected; and a fixed structure (27a, 27b), having fixed electrodes suspended above the substrate at the first area (24') of the surface and defining with the mobile structure a capacitive coupling to form at least one sensing capacitor, whose capacitance value is indicative of the quantity to be detected. A single mechanical-anchorage structure (32) provides anchoring of both the mobile structure and the fixed structure to the substrate at a second area (24") of the surface, distinct and separate from the first area (24'); connection elements (34a-34c) couple the mobile structure and the fixed structure mechanically to the single mechanical-anchorage structure.

公开(公告)号：EP3937317A1

公开(公告)日：2022-01-12

申请号：EP21305823.3

申请日：2021-06-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： LETOR, Romeo ,  POLETTO, Vanni ,  PAVLIN, Antoine ,  RUSSO, Alfio ,  LECCI, Nadia

IPC: H01S5/042 ,  H01S5/062 ,  H03K17/56 ,  G01S17/88

Abstract: A pulse generator circuit, for driving an array of laser diodes (LD_1, ..., LD_n) in a LIDAR system, for instance, comprises an LC resonant circuit (Lr, Cr) coupled between a first node (12) and a reference node (GND) as well as charge circuitry (16) configured to charge the capacitance (Cr) in the LC resonant circuit (Lr, Cr). A first electronic switch (S1) is coupled between the first node (12) and the reference node (GND), and one or more second electronic switches (S2_1, ..., S2_n) are coupled between the first node (12) and respective drive nodes (12 1 , ..., 12 n ) in turn configured to be coupled to respective electrical loads (LD_1, ..., LD_n).
The circuit comprises drive circuitry (18, 182_1, ..., 182_n; 201, 202, 203) configured to repeat pulse generation cycles comprising:
closing the first electronic switch (S1), to enable the LC resonant circuit (Lr, Cr) to oscillate with an increasing current flowing in the inductance (Lr) therein,
in response to the current flowing in the inductance (Lr) reaching a threshold value, opening the first electronic switch (S1) wherein, as a result of one second electronic switch (S2_1, ..., S2_n) being closed for a respective pulse duration time (Ton_S2_1, ..., Ton_S2_n), the current in the inductance (Lr) is commutated towards the aforesaid second electronic switch (S2_1, ..., S2_n) and the respective drive node (12 1 , ..., 12 n ),
opening the at least one second electronic switch (S2_1, ..., S2_n) at the expiration of said respective pulse duration time (Ton_S2_1, ..., Ton_S2_n).

公开(公告)号：EP3930007A1

公开(公告)日：2021-12-29

申请号：EP21180931.4

申请日：2021-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  MAGRI', Angelo ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36

Abstract: Electronic device (100) comprising: a semiconductor body (102) of silicon carbide; a body region (105) at a first surface of the semiconductor body; a source region (108) in the body region (105); a drain region (104) at a second surface of the semiconductor body (102); a doped region (120) extending seamlessly at the entire first surface (102a) of the semiconductor body (102) and including one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：EP3926829A1

公开(公告)日：2021-12-22

申请号：EP21177180.3

申请日：2021-06-01

Applicant: STMicroelectronics S.r.l.

Inventor： RAIMONDI, Mr. Marco ,  GONANO, Mr. Giovanni

IPC: H03K7/08 ,  H03F3/217 ,  H03K5/24

Abstract: A PWM modulator circuit (100) comprises a first half-bridge stage (121) having a first output node (OUTP) and a second half-bridge stage (122) having a second output node (OUTM). The first output node (OUTP) and the second output node (OUTM) are configured to have an electrical load (LD) coupled therebetween to apply thereto a PWM-modulated output signal. The circuit comprises a differential stage (10) having input nodes (InP, InM) configured to receive an input signal (an audio signal for a source S, for instance) applied between the input nodes (InP, InM) and produce a differential control signal (VcP, VcM) for the first half-bridge stage (121) and the second half-bridge stage (122). A current comparator (14) is arranged intermediate the differential stage (10) and the first (121) and second (122) half-bridge stages. The current comparator (14) is configured to produce a PWM-modulated drive signal (Drvin) to drive the half-bridge stages (121, 122) as a function of the input signal applied between the input nodes (InP, InM) in the differential stage (10).

公开(公告)号：EP3923683A1

公开(公告)日：2021-12-15

申请号：EP21177957.4

申请日：2021-06-07

Applicant: STMicroelectronics S.r.l.

Inventor： SEMINARA, Maria Francesca ,  MUSUMECI, Salvatore Rosario

IPC: H05B45/325

Abstract: A LED driver system (200) adapted to be coupled to an array of LEDs (102) for driving said array of LEDs is provided. The LED driver system comprises:
- a power transistor (N1) configured to be selectively activated for generating a driving current (Iset) for the array of LEDs, the power transistor having a first conduction terminal coupled to the array of LEDs (102) and a second conduction terminal coupled to a reference resistor (Rset);
- an operational amplifier (130) having a non-inverting input for receiving a reference voltage (Vref), an inverting input coupled to the second conduction terminal of the power transistor (N1) , and an output terminal coupled to a first conduction terminal of a transmission gate (TG1), said transmission gate having a second conduction terminal coupled to a control terminal of the power transistor (N1) and a control terminal for receiving an enable signal (ENA), said first and second conduction terminals of the transmission gate (TG1) being electrically connected to each other when the enable signal is at an enabling value to cause activation of said power transistor (N1) , and being electrically insulated from each other when the enable signal is at a disabling value to cause deactivation of said power transistor (N1);
- a slew rate control unit (210) configured to control the slew rate of the driving current (Iset), the slew rate control unit being configured to selectively charge an equivalent parasitic capacitance (C) at the control terminal of the power transistor (N1) through a charging current (Ich) and to selectively discharge said equivalent capacitance (C) through a discharging current (Idsch), said charging current and said discharging current depending at least in part on a target value ( Iset(h) ) of the driving current.