公开(公告)号：EP2214351A1

公开(公告)日：2010-08-04

申请号：EP10161294.3

申请日：2001-04-03

申请人： Mosaid Technologies Incorporated

发明人： Binder, Yehuda

IPC分类号： H04L12/40 ,  H04M11/06

CPC分类号： H04L12/2838 ,  H04B3/542 ,  H04B2203/5445 ,  H04L12/28 ,  H04L12/2803 ,  H04L12/2832 ,  H04L12/6418 ,  H04L12/66 ,  H04L2012/2841 ,  H04L2012/2843 ,  H04L2012/2845 ,  H04W4/04 ,  H04W4/18 ,  H04W16/20 ,  H04W80/00 ,  H04W84/12 ,  H04W84/14 ,  H04W92/02 ,  Y02B70/325 ,  Y02D70/142 ,  Y04S20/228

摘要： The invention provides a device for coupling at least first and second non-wired segments carrying first and second digital data signals thereover in first and second frequency bands, respectively, the device comprising a transceiver configured to perform first directional digital data communication of the first digital data signal over the first non-wired segment using a first digital data protocol, and to perform second directional digital data communication of the second digital data signal over the second non-wired segment using a second digital data protocol, and an adapter coupled with the transceiver for converting data between the first and second digital data protocols.

摘要翻译： 本发明提供了一种用于分别在第一和第二频带中耦合承载第一和第二数字数据信号的至少第一和第二非有线段的设备，该设备包括收发机，该收发机被配置为执行第一数字数据 使用第一数字数据协议在第一非有线段上的数据信号，并且使用第二数字数据协议在第二非有线段上执行第二数字数据信号的第二方向数字数据通信，以及与第 收发器，用于在第一和第二数字数据协议之间转换数据。

公开(公告)号：EP2154853A1

公开(公告)日：2010-02-17

申请号：EP09173023.4

申请日：1998-01-06

申请人： Mosaid Technologies Incorporated

发明人： Van Nee, Richard C. J.

IPC分类号： H04L27/26 ,  H04L1/12 ,  H04L5/14

CPC分类号： H04L27/2602 ,  H04L1/0002 ,  H04L5/1446 ,  H04L25/08 ,  H04L27/2605 ,  H04L27/2607 ,  H04L27/2647 ,  H04L27/2662

摘要： An OFDM system uses a normal mode which has a symbol length T, a guard time T G and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KT G where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.

摘要翻译： OFDM系统使用具有在时间T上正交的符号长度T，保护时间TG和一组N个子载波的正常模式，以及具有符号长度KT和保护时间KT的一个或多个回退模式 其中K是大于1的整数。 相同的N个子载波组用于回退模式，与正常模式一样。 由于使用相同的子载波集合，所以总带宽基本上是恒定的，所以别名滤波不需要是自适应的。 傅里叶变换操作与正常模式相同。 因此，回退模式的硬件成本很低。 在回退模式中，增加的保护时间提供更好的延迟扩展容限，并且增加的符号长度提供改善的信噪比性能，并因此提高了范围，以降低的数据速率为代价。

公开(公告)号：EP2150958A1

公开(公告)日：2010-02-10

申请号：EP08748199.0

申请日：2008-04-28

申请人： Mosaid Technologies Incorporated

发明人： PYEON, Hong Beom

IPC分类号： G11C7/10 ,  G11C11/40 ,  G11C11/41 ,  G11C11/413 ,  G11C16/02 ,  G11C7/12

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5642 ,  G11C2211/5647

摘要： An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

摘要翻译： 提供了一个访问缓冲区，例如页面缓冲区，用于使用两阶段MLC（多级单元）操作写入非易失性存储器，如Flash。 访问缓冲区具有用于临时存储要写入的数据的第一锁存器。 提供第二个锁存器用于从存储器读取数据，作为两阶段写入操作的一部分。 当从存储器读取时，第二锁存器具有参与锁存功能的反相器。 使用相同的反相器来产生写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。

公开(公告)号：EP2132748A1

公开(公告)日：2009-12-16

申请号：EP08714575.1

申请日：2008-02-08

申请人： Mosaid Technologies Incorporated

发明人： PYEON, Hong Beom

IPC分类号： G11C8/12 ,  G11C16/02 ,  G11C7/24 ,  G11C8/20

CPC分类号： G11C16/08 ,  G11C8/12 ,  G11C8/20 ,  G11C16/16

摘要： Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

公开(公告)号：EP2122626A1

公开(公告)日：2009-11-25

申请号：EP07855449.0

申请日：2007-12-03

申请人： MOSAID Technologies Incorporated

发明人： PYEON, Hong Beom ,  OH, Hak June ,  KIM, Jin-Ki ,  PRZYBYLSKI, Steven A.

IPC分类号： G11C8/18 ,  G11C16/02 ,  G11C8/04 ,  G11C8/06

CPC分类号： G11C7/20 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1003 ,  G11C19/00 ,  G11C2029/4402

摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

公开(公告)号：EP2118903A1

公开(公告)日：2009-11-18

申请号：EP07855464.9

申请日：2007-12-04

申请人： MOSAID Technologies Incorporated

发明人： OH, HakJune ,  PYEON, Hong Beom ,  KIM, Jin-Ki

IPC分类号： G11C8/18 ,  G06F12/00 ,  G11C11/34 ,  G11C16/02 ,  G11C8/04 ,  G11C8/06

CPC分类号： G11C16/08 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/20

摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

公开(公告)号：EP2100306A1

公开(公告)日：2009-09-16

申请号：EP07855586.9

申请日：2007-12-18

申请人： Mosaid Technologies Incorporated

发明人： KIM, Jin-Ki

IPC分类号： G11C7/10 ,  G06F12/00 ,  G06F13/14 ,  G11C11/4063 ,  G11C11/413 ,  G11C7/20

CPC分类号： G11C14/0018 ,  G11C11/005

摘要： A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

公开(公告)号：EP2074623A1

公开(公告)日：2009-07-01

申请号：EP07800456.1

申请日：2007-08-20

申请人： Mosaid Technologies Incorporated

发明人： KIM, Jin-Ki ,  OH, HakJune ,  PYEON, Hong Beom

IPC分类号： G11C8/00 ,  G06F12/02 ,  G06F13/14 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12

CPC分类号： G06F13/4243 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10

摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

公开(公告)号：EP1955333A1

公开(公告)日：2008-08-13

申请号：EP06817678.3

申请日：2006-11-30

申请人： Mosaid Technologies Incorporated

发明人： OH, HakJune

IPC分类号： G11C11/4063 ,  G11C11/4074 ,  G11C11/4093

CPC分类号： G11C11/406 ,  G11C8/10

摘要： A dynamic random access memory has logically identical circuits for providing the same logical control signals. Each set of control signals can have different electrical parameters. One circuit can be optimized for high speed performance, while another circuit can be optimized for low power consumption. The logically identical circuits can include wordline address predecoder circuits, where a high speed predecoder circuit is enabled during a normal operating mode and a slower low power predecoder circuit is enabled for self-refresh operations. During self-refresh operations, the high speed circuit can be decoupled from the power supply to minimize its current leakage.

公开(公告)号：EP1932158A1

公开(公告)日：2008-06-18

申请号：EP06790773.3

申请日：2006-09-29

申请人： Mosaid Technologies Incorporated

发明人： OH, HakJune ,  PYEON, Hong, Beom ,  KIM, Jin-Ki

IPC分类号： G11C11/4197 ,  G11C11/4093 ,  G11C11/4063 ,  G11C16/26

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制对半导体存储器中的串行数据链路接口的输出端口的数据传输的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使存储器件能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储器组，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。