公开(公告)号：EP2067265A4

公开(公告)日：2013-06-26

申请号：EP07798752

申请日：2007-06-19

Applicant: FREESCALE SEMICONDUCTOR INC

Inventor： HE ZHONGLI

IPC: H04B1/66 ,  H04N7/12 ,  H04N7/26 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/117 ,  H04N19/119 ,  H04N19/136 ,  H04N19/156 ,  H04N19/176 ,  H04N19/186 ,  H04N19/56 ,  H04N19/70 ,  H04N19/82 ,  H04N19/86 ,  H04N19/865

公开(公告)号：EP2338168A4

公开(公告)日：2013-06-12

申请号：EP09822395

申请日：2009-09-29

Applicant: FREESCALE SEMICONDUCTOR INC

Inventor： HERRICK MATTHEW T ,  CHANG KO-MIN ,  CHINDALORE GOWRISHANKAR L ,  KANG SUNG-TAEG

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

公开(公告)号：EP2589152A1

公开(公告)日：2013-05-08

申请号：EP10749489.0

申请日：2010-06-29

Applicant: Freescale Semiconductor, Inc.

Inventor： GEYNET, Lionel ,  VIGUIER, Jean-Stéphane

IPC: H03L7/099

CPC classification number: H03L7/00 ,  H03B5/04 ,  H03B5/124 ,  H03L1/00 ,  H03L1/023 ,  H03L7/099 ,  H03L7/10

Abstract: An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.

公开(公告)号：EP2586127A1

公开(公告)日：2013-05-01

申请号：EP11807201.6

申请日：2011-05-09

Applicant: Freescale Semiconductor, Inc.

Inventor： STOCKINGER, Michael A. ,  CAMARENA, Jose A. ,  ZHANG, Wenzhong

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K17/102

Abstract: A transmission gate circuit includes a first transmission gate, having a first switching device, coupled in series with a second transmission gate, having a second switching device, and control circuitry which places the first transmission gate and the second transmission gate into a conductive state to provide a conductive path through the first transmission gate and the second transmission gate. When the voltage of the first terminal is above a first voltage level and outside a safe operating voltage area of at least one of the first and second switching device, the first switching device remains within its safe operating voltage area and the second switching device remains within its safe operating voltage area.

公开(公告)号：EP2497258A4

公开(公告)日：2013-05-01

申请号：EP09851060

申请日：2009-11-06

Applicant: FREESCALE SEMICONDUCTOR INC

Inventor： KRUTSCH ROBERT ,  PRALEA RADU D

IPC: H04M3/56

CPC classification number: H04M3/569 ,  H04M3/566 ,  H04M2203/5072 ,  H04M2242/06

Abstract: A conference call system comprises an input interface for receiving during a conference call at least two input streams of audio signal, each from another source. A selection unit is connected to the input interface, for selecting a number of dominant speaker streams out of the input streams, the number being less than or equal to a maximum number of dominant speakers value and each of the dominant speaker streams representing speech from a respective dominant speaker. A mixer is connected to the selection unit, for mixing the selected streams into an output stream. The conference call system comprises an output interface for outputting the output stream and a selection control unit connected to the selection unit and the input interface, for dynamically setting, during the conference call, the maximum number of dominant speakers value based on dynamics of the conference call.

Abstract translation: 电话会议系统包括输入接口，用于在电话会议期间接收至少两个音频信号的输入流，每个来自另一个源。 选择单元连接到输入接口，用于从输入流中选择多个主要扬声器流，该数量小于或等于主要扬声器值的最大数量，并且每个主要扬声器流表示来自 各自的主导言论者。 混合器连接到选择单元，用于将所选择的流混合成输出流。 电话会议系统包括用于输出输出流的输出接口和连接到选择单元和输入接口的选择控制单元，用于在电话会议期间基于会议的动态动态地设定主要扬声器的最大数量 呼叫。

公开(公告)号：EP1869855A4

公开(公告)日：2013-05-01

申请号：EP06736439

申请日：2006-02-28

Applicant: FREESCALE SEMICONDUCTOR INC

Inventor： RAHMAN MAHIBUR ,  SHAH MANISH N ,  SOBCHAK CHARLES L

IPC: H04L27/08 ,  H04L25/06

CPC classification number: H04L25/061 ,  H03D3/008 ,  H03G3/3068 ,  H04B1/30

公开(公告)号：EP2229730B1

公开(公告)日：2013-04-24

申请号：EP07849357.4

申请日：2007-12-06

Applicant: Freescale Semiconductor, Inc.

Inventor： ROTH, Andreas ,  BODE, Hubert ,  LAUDENBACH, Andreas ,  LEHMANN, Stephan ,  WITTICH, Engelbert

IPC: H03K17/0814 ,  H03K19/003

CPC classification number: H03K19/00346 ,  G06F21/755

公开(公告)号：EP2580703A1

公开(公告)日：2013-04-17

申请号：EP10852816.7

申请日：2010-06-11

Applicant: Freescale Semiconductor, Inc.

Inventor： CLOETENS, Henri

IPC: G06F21/24 ,  G06F11/10 ,  G06F12/00

CPC classification number: G06F11/1028 ,  G06F21/64 ,  G06F21/79

Abstract: A method (400) for providing data protection for data stored within a Random Access Memory (RAM) element. The method comprises receiving data to be written to memory (420), dividing the received data into a plurality of data sections (430), applying error correction codes to the data sections to form codeword sections (440), interleaving the codeword sections to form an interleaved data codeword (450), and writing within a single clock cycle the interleaved data codeword to memory (460).

公开(公告)号：EP2578994A2

公开(公告)日：2013-04-10

申请号：EP12186133.0

申请日：2012-09-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Lin, Yizhen

IPC: G01C19/5712

CPC classification number: G01C19/5712

Abstract: A rotary disk gyroscope (20) includes a drive mass (28) and a sense mass (32). The sense mass (32) includes a cutout region (46, 48) located proximate an axis of rotation (40). Torsion springs (38), located in the cutout region (46, 48), connect the sense mass (32) to the drive mass (28). The torsion springs (38) enable the sense mass (32) to rotate about the axis of rotation (40) in response to an angular velocity of the gyroscope (20). Spring anchorage structures (30) are also positioned in the cutout region (46, 48), and flexibly couple the drive mass (28) to the substrate (22). In addition, a drive system (68) resides in the cutout region (46, 48) and actuates the drive mass (28) to move with an oscillatory motion. In a dual axis configuration, the gyroscope (20) further includes a rectangular-shaped second sense mass (36) surrounding the disk-shaped drive mass (28).

Abstract translation: 旋转盘陀螺仪（20）包括驱动块（28）和感测块（32）。 感测质量块（32）包括邻近旋转轴线（40）定位的切口区域（46,48）。 位于切口区域（46,48）中的扭转弹簧（38）将感测质量块（32）连接到驱动质量块（28）。 扭转弹簧（38）使得感测质量（32）能够响应于陀螺仪（20）的角速度围绕旋转轴线（40）旋转。 弹簧锚固结构（30）也定位在切口区域（46,48）中，并且将驱动块（28）柔性地联接到基板（22）上。 此外，驱动系统（68）位于切口区域（46,48）中，并致动驱动块（28）以振荡运动移动。 在双轴构造中，陀螺仪（20）还包括围绕盘形驱动块（28）的矩形的第二感测质量块（36）。

公开(公告)号：EP2577422A2

公开(公告)日：2013-04-10

申请号：EP11787069.1

申请日：2011-04-20

Applicant: Freescale Semiconductor, Inc.

Inventor： RAMARAJU, Ravindraraj ,  BEARDEN, David, R. ,  COOPER, Troy, L.

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/171

Abstract: A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.