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    Method for making a high performance transistor integrated circuit and the resulting integrated circuit
    81.
    发明公开
    Method for making a high performance transistor integrated circuit and the resulting integrated circuit 失效
    制造集成电路晶体管高效率的方法和所得到的集成电路。

    公开(公告)号：EP0139130A1

    公开(公告)日：1985-05-02

    申请号：EP84109402.2

    申请日：1984-08-08

    申请人： International Business Machines Corporation

    发明人： Lechaton, John S. ,  Pitner, Philip Michael ,  Srinivasan, Gurumakonda Ramasamiengar

    IPC分类号： H01L21/00 ,  H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/7325 ,  H01L29/1004 ,  Y10S148/01

    摘要： 57 A high performance NPN bipolar transistor functioning in a current switch logic circuit is formed within an isolated region of a monocrystalline silicon body (10) wherein the transistor includes an N+ subcollector (12), an N+ collector reach-through (20) which connects the subcollector to a major surface of the silicon body, a P base region (22) above the subcollector and adjacent to the reach-through region, an N emitter region (30) within the base region and extending from the major surface. The base region (22) includes an intrinsic base region located below the emitter region (30) and an extrinsic region (34) located extending from the major surface and adjacent to the emitter region. The extrinsic base preferably completely surrounds or rings the emitter region. Using a mask (32) with openings (24) only in the areas of the extrinsic base regions a P+ type region (34) is formed by ion implanting with a P type dopant to a depth of less than the depth of the N emitter region (30) followed by a short thermal anneal to activate the P dopant. By the independent control of the intrinsic and extrinsic base resistances the performance of bipolar transistor integrated circuits for current switch logic applications is substantially increased.

    摘要翻译： 高性能NPN双极型晶体管中的电流开关逻辑电路发挥作用在上N +集电极的到达 - - （20）的单晶硅主体（10）worin所述晶体管包括在N +子集电极（12）的分离的区域内形成有连接所述 子集电极至硅本体，子集电极和毗邻到达通过区域上方的P基极区域（22），在基极区域内的N +发射极区（30）的一个主要表面和从所述主表面延伸。 基极区域（22）包括位于从所述主表面和毗邻所述发射极区域延伸位于下方的发射极区（30）和上外源性区域（34）本征基区。 非本征基极优选地完全包围电话或圆形的发射极区域。 仅使用所述非本征基极区的面积的P +型区域的掩模（32）有开口（24）（34）由离子与P型掺杂剂注入到的深度小于所述N个的发射极区的深度来形成 （30），随后通过短的热退火，以激活掺杂剂P. 由内在和外在的基极termoresistencias的独立控制双极晶体管集成电路的电流开关逻辑应用程序的性能显着增加。

    Method for making a high performance bipolar transistor in an integrated circuit
    82.
    发明公开
    Method for making a high performance bipolar transistor in an integrated circuit 失效
    一种用于在集成电路中制造高品质的双极型晶体管的方法。

    公开(公告)号：EP0089503A2

    公开(公告)日：1983-09-28

    申请号：EP83101755.3

    申请日：1983-02-23

    申请人： International Business Machines Corporation

    发明人： Gaur, Santosh Prasad ,  Lechaton, John S. ,  Srinivasan, Gurumakonda R.

    IPC分类号： H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/1004 ,  H01L21/3065 ,  H01L29/7325

    摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

    A self-aligned process for providing an improved high performance bipolar transistor
    85.
    发明公开
    A self-aligned process for providing an improved high performance bipolar transistor 失效
    自对准用于制造改进的高品质的双极型晶体管的过程。

    公开(公告)号：EP0036082A1

    公开(公告)日：1981-09-23

    申请号：EP81101068.5

    申请日：1981-02-16

    申请人： International Business Machines Corporation

    发明人： Horng, Cheng Tzong

    IPC分类号： H01L21/00 ,  H01L21/285 ,  H01L21/60 ,  H01L21/76 ,  H01L29/72

    CPC分类号： H01L21/76897 ,  H01L21/033 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/66272 ,  H01L29/7325 ,  Y10S148/131

    摘要： Disclosed is a self-aligned process for providing an improved high-performance bipolar transistor. The transistor device region is isolated from the other devices on the wafer by a wide deep oxide trench (16). The deep oxide trench which has nearly vertical sidewalls, extends from the epitaxial silicon surface through the N * subcollector region into the P-substrate. A shallow oxide trench is used to separate the collector reach through region from the base region. A heavily doped polysilicon layer is used to dope and make contact to the transistor base as well as define the emitter window (28) through which the emitter is doped. In the structure, the separation between the emitter contact and the polysilicon base contact is reduced to a very small value. This is achieved by employing the self-aligned process in accordance with the invention. Metal contact to the polysilicon base contact is done over the deep trench oxide isolation. This allows the transistor base area, and hence the collector base capacitance to be minimized. The shallow emitter and narrow base width of the transistor are formed by ion implantations.

    Semiconductor devices and method for producing the same
    86.
    发明公开
    Semiconductor devices and method for producing the same 失效
    半导体器件及其制备方法。

    公开(公告)号：EP0019456A1

    公开(公告)日：1980-11-26

    申请号：EP80301576.7

    申请日：1980-05-14

    申请人： FUJITSU LIMITED

    发明人： Kawabe, Yunosuke ,  Momma, Yoshinobu

    IPC分类号： H01L21/76 ,  H01L29/72 ,  H01L29/06

    CPC分类号： H01L21/763 ,  H01L21/76 ,  H01L21/76227 ,  H01L29/7325 ,  Y10S148/085 ,  Y10S148/117

    摘要： In a semiconductor device comprising at least one bipolar transistor (45) and a VIP isolating layer (43) which are formed in both an epitaxial layer (33) and a semiconductor substrate (31), an impurity-introduced region (37) having the same conductivity type as that of the semiconductor substrate (31) is formed so asto surround the V-groove (36). A buried layer (32) of the bipolartransistor comes into contact with the VIP isolating layer (39,40) to divide the impurity-intorduced region into two parts, one of which is combined with a base region (37) and the other one of which serves as a channel stopper (38).

    Procédé de fabrication d'un transistor bipolaire de type MESA présentant des régions d'émetteur et de base auto-alignées
    88.
    发明公开
    Procédé de fabrication d'un transistor bipolaire de type MESA présentant des régions d'émetteur et de base auto-alignées 失效
    一种用于制造具有自对准发射极和基极区的台面双极型晶体管的方法。

    公开(公告)号：EP0004292A2

    公开(公告)日：1979-10-03

    申请号：EP79100546.5

    申请日：1979-02-23

    申请人： International Business Machines Corporation

    发明人： Ning, Tak Hung ,  Yu, Hwa-Nien

    IPC分类号： H01L21/00 ,  H01L29/10 ,  H01L29/72

    CPC分类号： H01L21/033 ,  H01L29/1004 ,  H01L29/7325

    摘要： Ce transistor est réalisé à partir d'une structure classique comportant un substrat (21), une région de sous-collecteur (22) associée à une région de traversée de collecteur (24), une couche épitaxiale (20) servant de région de collecteur et une couche de base (26) et des murs d'isolement (23). Dans un mode préféré on forme une couche d'émetteur (27) sur la couche de base. Puis une couche de masquage (28) est formée sur la couche d'émetteur, elle définit une ouverture autour de la région destinée à constituer l'émetteur. Les parties exposées de la structure sont attaquées ce qui définit avec précision la région d'émetteur (27), et la région de base (26). On forme alors par implantation ionique la région de contact de base (32). Les régions d'émetteur, de base et de contact de base sont donc auto-alignées. La structure est passivée par les régions d'oxyde encastré (33). On forme enfin les contacts ohmiques nécessaires. Ce procédé permet l'obtention de transistors très rapides et à grande densité d'intégration utiles dans les applications aux calculateurs.

    摘要翻译： 此晶体管是从常规的结构，其包括与外延层的作为集电区和基极层（26）和绝缘集电极通道区（24）（20）相关联的基板（21），一个子集电极区域（22）而形成 壁（23）。 在一个优选实施方案，对发射极层（27）是形成在所述基底层上。 然后掩蔽层（28）形成在发射极层上; 它定义在用于构成发射极的区域周围开幕。 该结构的外露部分被攻击; 此精确地设定定义发射极区域（27）和基极区（26）。 然后离子注入用于形成基极接触区（32）。 发射极，基极和基极接触区自对准THUS。 结构由埋入的氧化（33）的区域钝化。 最后，所需的电阻接触形成。 这种方法可使制造具有高集成密度在计算机的应用程序是有用的非常快的晶体管。

    TRENCH-ISOLATED BIPOLAR DEVICES
    89.
    发明授权
    TRENCH-ISOLATED BIPOLAR DEVICES 失效
    通过沟槽INSULATED双极组件

    公开(公告)号：EP0970518B1

    公开(公告)日：2012-04-25

    申请号：EP98911328.7

    申请日：1998-03-18

    申请人： Infineon Technologies AG

    发明人： NORSTRÖM, Hans ,  TYLSTEDT, Ola, Knut ,  LINDGREN, Anders

    IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/331 ,  H01L29/417 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L21/76224 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/7325

    摘要： In order to produce an electrical connection to an inner layer such as a bottom diffusion (103), which has a good electrical conductivity and is located inside a bipolar semiconductor device isolated by trenches (119) and which for example forms a subcollector of a NPN-transistor, a hole (157) in a trench is used. The hole is filled with electrically conducting material and extends from the surface of the device to the bottom diffusion (103), so that the electrically conducting material in the hole is in contact therewith. The hole (157) is made aligned with a sidewall of the trench (119) by using selective etching. The hole can be made at the same time as contact holes for metallization are made and then also be filled in the metallization step, to contact the bottom diffusion. For a lateral PNP-transistor the hole can be made as a closed groove constituting the outer confinement of the base area, passing all around the transistor. The outer sidewall of such a closed trench can, as seen from above, be bevelled by 45°, so that no inner corners having too small angles are found in the trench, what facilitates the filling with oxide.