公开(公告)号：EP1992050A1

公开(公告)日：2008-11-19

申请号：EP07748987.0

申请日：2007-01-17

申请人： CREE, INC.

发明人： IBBETSON, James, P. ,  KELLER, Bernd, P. ,  MISHRA, Umesh, K.

IPC分类号： H01S5/042 ,  H01L33/00

CPC分类号： H01L33/04 ,  H01L33/0016 ,  H01L33/08 ,  H01L33/32

摘要： An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.

公开(公告)号：EP1665358A2

公开(公告)日：2006-06-07

申请号：EP04788636.1

申请日：2004-09-09

申请人： The Regents of the University of California ,  CREE, INC.

发明人： CHINI, Alessandro ,  MISHRA, Umesh, K. ,  PARIKH, Primit ,  WU, Yifeng

IPC分类号： H01L21/338 ,  H01L31/072 ,  H01L27/095 ,  H01L23/58

CPC分类号： H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/785

摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

公开(公告)号：EP1579509A1

公开(公告)日：2005-09-28

申请号：EP03800265.5

申请日：2003-12-23

申请人： CREE, INC.

发明人： MISHRA, Umesh, K. ,  PARIKH, Primit ,  WU, Yifeng

IPC分类号： H01L29/778 ,  H01L21/60 ,  H01L23/36

CPC分类号： H05K1/0206 ,  H01L21/8252 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/181 ,  H05K2201/066 ,  Y10T29/4913 ,  H01L2924/0002 ,  H01L2924/00

摘要： A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it.; An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals. The present invention is particularly applicable to Group III nitride based active semiconductor devices grown on SiC substrates. The passive components and interconnects can then be formed on a lower cost, higher diameter wafer made of GaAs or Si. After separation, the Group III devices can be flip-chip mounted on the GaAs or Si substrate.