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    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
    4.
    发明公开
    METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS 审中-公开
    金属布线结构以集成到基片中的孔

    公开(公告)号：EP2313921A4

    公开(公告)日：2014-08-27

    申请号：EP09805365

    申请日：2009-07-28

    Applicant: IBM

    Inventor： COLLINS DAVID S ,  JOSEPH ALVIN ,  LINDGREN PETER J ,  STAMPER ANTHONY K ,  WATSON KIMBALL M

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER
    5.
    发明公开
    THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 有权
    ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER ER

    公开(公告)号：EP2250669A4

    公开(公告)日：2012-07-25

    申请号：EP09710899

    申请日：2009-02-11

    Applicant: IBM

    Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

    Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

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