公开(公告)号：EP3155658A4

公开(公告)日：2018-02-28

申请号：EP14895276

申请日：2014-06-16

申请人： INTEL CORP

发明人： NELSON DONALD W ,  WEBB M CLAIR ,  MORROW PATRICK ,  JUN KIMIN

IPC分类号： H01L27/06 ,  H01L21/60 ,  H01L23/12

CPC分类号： H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

摘要： A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

公开(公告)号：EP3155653A4

公开(公告)日：2018-02-21

申请号：EP14894875

申请日：2014-06-16

申请人： INTEL CORP

发明人： NELSON DONALD W ,  WEBB M CLAIR ,  MORROW PATRICK ,  JUN KIMIN

IPC分类号： H01L27/06 ,  H01L21/335 ,  H01L29/78

CPC分类号： H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014

摘要： A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

公开(公告)号：EP3155654A4

公开(公告)日：2018-06-27

申请号：EP14895326

申请日：2014-06-16

申请人： INTEL CORP ,  NELSON DON W ,  WEBB MILTON CLAIR ,  MORROW PATRICK ,  JUN KIMIN

发明人： NELSON DONALD W ,  WEBB M CLAIR ,  MORROW PATRICK ,  JUN KIMIN

IPC分类号： H01L21/336 ,  H01L21/98 ,  H01L25/065 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L25/0652 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/8221 ,  H01L23/427 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/0922 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/00

摘要： A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.