公开(公告)号：EP4391037A1

公开(公告)日：2024-06-26

申请号：EP22214863.7

申请日：2022-12-20

申请人： Imec VZW ,  Katholieke Universiteit Leuven KU Leuven Research & Development

发明人： CHAN, Boon Teik ,  SALAHUDDIN, Shairfe Muhammad ,  RYCKAERT, Julien ,  CHEHAB, Bilal ,  LIU, Hsiao-Hsuan

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823878 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L21/823807 ,  H01L29/42392 ,  H01L29/66772

摘要： The disclosure relates to a method for forming a semiconductor device, comprising:
forming a device structure (400) on a substrate (102), the device structure comprising:
a device layer stack comprising a bottom device sub-stack comprising at least one bottom channel layer (124), and a top device sub-stack comprising at least one top channel layer,
a sacrificial gate structure extending across the device layer stack, and
bottom source/drain structures (126a, 126b) on opposite ends of the at least one bottom channel layer;

forming an opening exposing the top device sub-stack, wherein forming the opening comprises etching the sacrificial gate structure;
forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening, wherein the etching extends through each of the at least one top channel layer and is stopped over the bottom device sub-stack; and
subsequent to forming the cut, forming a functional gate stack (480) on the at least one bottom channel layer.

公开(公告)号：EP4199112A1

公开(公告)日：2023-06-21

申请号：EP21215370.4

申请日：2021-12-17

申请人： IMEC VZW

发明人： CHAN, Boon Teik ,  VANDOOREN, Anne ,  RYCKAERT, Julien ,  HORIGUCHI, Naoto

IPC分类号： H01L29/775 ,  H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00

摘要： The disclosure relates to a method for forming a semiconductor device, the method comprising:
forming a device layer stack on a substrate, the device layer stack comprising:
- a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and
- a second sub-stack on the first sub-stack and comprising a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer,

wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and
wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack.
The method comprises replacing the second sacrificial layer of the second sub-stack with a dielectric layer; forming recesses in the device layer stack by laterally etching back end surfaces of the first sacrificial layers of the first and second sub-stacks from opposite sides of the sacrificial gate structure; and forming inner spacers in the recesses.

公开(公告)号：EP3772091A1

公开(公告)日：2021-02-03

申请号：EP19189796.6

申请日：2019-08-02

申请人： Imec VZW

发明人： DENTONI LITTA, Eugenio ,  GUPTA, Anshul ,  RYCKAERT, Julien ,  CHAN, Boon Teik

IPC分类号： H01L21/74 ,  H01L23/528

摘要： According to an aspect of the present inventive concept there is provided a method for forming a buried metal line in a substrate, the method comprising:
at a position between a pair of semiconductor structures protruding from the substrate, forming a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair, wherein forming the metal line trench comprises:
etching an upper trench portion in the substrate,
forming a spacer on sidewall surfaces of the upper trench portion, the spacer exposing a bottom surface of the upper trench portion, and
while the spacer masks the sidewall surfaces of the upper trench portion, etching a lower trench portion, comprising etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion, and

forming the metal line in the metal line trench.

公开(公告)号：EP3671821A1

公开(公告)日：2020-06-24

申请号：EP18214146.5

申请日：2018-12-19

申请人： IMEC VZW

发明人： COSEMANS, Stefan ,  RYCKAERT, Julien ,  TOKEI, Zsolt

IPC分类号： H01L21/768 ,  H01L23/528

摘要： Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines (20, 21, 22, 23), said multilevel layer comprising at least three levels (L0, L1, L2) forming a centerline level (L1), an upper extension line level (L2) and a lower extension line level (L0) said levels providing multilevel routing tracks in which said lines extend.

公开(公告)号：EP3244447A1

公开(公告)日：2017-11-15

申请号：EP16169098.7

申请日：2016-05-11

申请人： IMEC VZW

发明人： RAGNARSSON, Lars-Åke ,  DEKKERS, Hendrik F. W. ,  SCHRAM, Tom ,  RYCKAERT, Julien ,  HORIGUCHI, Naoto ,  BADAROGLU, Mustafa

IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L21/823857 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L29/66545

摘要： According to an aspect of the present inventive concept there is provided a method for forming a gate structure at a first set of one or more semiconductor features and a second set of one or more semiconductor features, wherein a dummy gate extends across the semiconductor features of the first set and the semiconductor features of the second set, the method comprising:
forming a hole by etching the dummy gate wherein the dummy gate is divided into a first dummy gate section and a second dummy gate section,
forming a barrier in said hole by depositing a barrier material in said hole,
removing the first dummy gate section and the second dummy gate section by etching wherein a first trench section is formed and a second trench section is formed,
forming a first gate conductor in the first trench section and the second trench section,
forming a mask above the second trench section, the mask exposing the first trench section,
etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and
forming a second gate conductor in the first trench section.

摘要翻译： 根据本发明构思的一个方面，提供了一种用于在第一组一个或多个半导体部件和第二组一个或多个半导体部件处形成栅极结构的方法，其中伪栅极延伸穿过 所述第一组和所述第二组的半导体特征，所述方法包括：通过蚀刻所述虚设栅极形成孔，其中所述虚设栅极被分成第一虚设栅极部分和第二虚设栅极部分，通过在所述孔中形成阻挡层 在所述孔中沉积阻挡材料，通过刻蚀去除第一虚设栅极部分和第二虚设栅极部分，其中形成第一沟槽部分并形成第二沟槽部分;在第一沟槽部分中形成第一栅极导体， 在所述第二沟槽部分上方形成掩模，所述掩模暴露所述第一沟槽部分，蚀刻所述第一沟槽部分中的所述第一栅极导体，w 这里掩模和阻挡层抵消第二沟槽部分中的第一栅极导体的蚀刻，并且在第一沟槽部分中形成第二栅极导体。

公开(公告)号：EP4191653A1

公开(公告)日：2023-06-07

申请号：EP21211959.8

申请日：2021-12-02

申请人： Imec VZW

发明人： CHEHAB, Bilal ,  SCHUDDINCK, Pieter ,  RYCKAERT, Julien ,  WECKX, Pieter

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/06 ,  H01L29/775 ,  H01L27/092

摘要： The disclosure relates to a complementary field-effect transistor, CFET, device (100)comprising:
a bottom FET device and a top FET device stacked on top of the bottom FET device,
the bottom FET device comprising a bottom gate electrode comprising a side gate portion arranged along a first side surface of the bottom channel nanostructure, and
the top FET device comprising a first and second channel layer spaced apart along the first direction, and a top gate electrode configured to define a tri-gate with respect to each of the first and second channel layers and comprising a common gate portion arranged between the first and second channel layers, and a pair of first gate prongs protruding in the first direction, and a pair of second gate prongs protruding in an opposite second direction,
wherein the side gate portion of the bottom gate electrode defines a via contact portion protruding outside the top gate electrode and the first channel layer of the top FET device; and

a top gate contact via for coupling the top gate electrode to a first conductive line over the top FET device and a bottom gate contact via for coupling the via contact portion of the bottom gate electrode to a second conductive line over the top FET device.

公开(公告)号：EP3840054A1

公开(公告)日：2021-06-23

申请号：EP19218708.6

申请日：2019-12-20

申请人： Imec VZW

发明人： DENTONI LITTA, Eugenio ,  BOEMMELS, Juergen ,  RYCKAERT, Julien ,  HORIGUCHI, Naoto ,  WECKX, Pieter

IPC分类号： H01L29/06 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H01L21/336 ,  H01L29/775

摘要： A method for forming a semiconductor device comprising forming a first transistor structure (10a) and a second transistor structure (20a) separated by a first trench which comprises a first dielectric wall (108) protruding above a top surface of the transistor structures. The first and the second transistor structures each comprise a plurality of stacked nanosheets (102a-b) forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further comprises depositing a contact material (136) over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion (120) of the first transistor structure and a first source/drain portion (124) of the second transistor structure. Further, the method comprises etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact (112a) contacting the first source/drain portion of the first transistor structure, and a second contact (112b) contacting the first source/drain portion of the second transistor structure.

公开(公告)号：EP3581543A1

公开(公告)日：2019-12-18

申请号：EP18178065.1

申请日：2018-06-15

申请人： IMEC vzw

发明人： WECKX, Pieter ,  BOEMMELS, Juergen ,  RYCKAERT, Julien

IPC分类号： B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L27/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L27/11

摘要： According to an inventive aspect there is provided a semiconductor device comprising:
first and second sets of transistors (100, 200) comprising a pass transistor (110, 210) and a stacked complementary transistor pair (120, 220) of a lower transistor (122, 222) and an upper transistor (124, 224),
wherein first transistor comprises a semiconductor channel (110c, 122c, 124c) extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a separate second fin track parallel to the first fin track, and
wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level,
a first tall gate electrode (130) forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and
a first short gate electrode (140) forming a gate for the first pass transistor and arranged along a second gate track,
a second tall gate electrode (230) forming a common gate for the second complementary transistor pair and arranged along the second gate track,
a second short gate electrode (240) forming a gate for the second pass transistor and arranged along the first gate track,
first and second contact arrangements (150, 250) forming a common drain contact for the transistors of the first set and the second set, respectively, and
first and second cross-couple contacts (170, 270) extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

公开(公告)号：EP3309789A1

公开(公告)日：2018-04-18

申请号：EP17195862.2

申请日：2017-10-11

申请人： IMEC vzw

发明人： VAN HOUDT, Jan ,  RYCKAERT, Julien ,  OH, Hyungrock

IPC分类号： G11C11/405 ,  G11C11/4097

CPC分类号： H01L27/108 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L21/8254 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/10805 ,  H01L28/60

摘要： According to an aspect of the present inventive concept there is provided a memory device for a dynamic random access memory, DRAM, comprising:
a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed,
an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices,
a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells, each bit cell including:
a charge storage element, a write transistor and a read transistor, wherein the write transistor includes a gate electrode connected to a write select line and a first electrode connected to a write bit line, wherein the charge storage element includes a first portion connected to a read select line and a second portion connected to a second electrode of the write transistor and to a gate electrode of the read transistor, and wherein the read transistor includes an electrode connected to a sense line,

a driver circuitry adapted to during a read mode apply a voltage to a read select line connected to a bit cell such that a gate voltage of the read transistor of said bit cell, on a condition that a first charge is stored by the charge storage element of said bit cell, is shifted to a first voltage which is smaller than a threshold voltage of the read transistor and, on a condition that a second charge is stored by the charge storage element of said bit cell, is shifted to a second voltage which is equal to or greater than the threshold voltage of the read transistor, and
a plurality of gain transistors formed in said semiconductor device layer, each gain transistor being connected to a respective one of said bit stacks via the sense lines connected to the read transistor of each bit cell of said respective bit stack and being adapted to output an amplified read out signal.

摘要翻译： 根据本发明构思的一个方面，提供了一种用于动态随机存取存储器DRAM的存储器件，包括：支撑半导体器件层的衬底，其中形成多个半导体器件;互连部分，形成在衬底上方 并且包括多个金属化层和介电层，互连部分适于互连所述半导体器件，多个位于互连部分中的位单元堆叠，每个位单元堆叠包括多个位单元，每个位单元包括： 电荷存储元件，写入晶体管和读取晶体管，其中所述写入晶体管包括连接到写入选择线的栅极电极和连接到写入位线的第一电极，其中所述电荷存储元件包括连接到 读取选择线和连接到写入晶体管的第二电极的第二部分，以及t 所述读取晶体管的栅极电极，并且其中所述读取晶体管包括连接到读出线的电极，适于在读取模式期间的驱动器电路向与位单元连接的读取选择线施加电压， 在所述位单元的电荷存储元件存储第一电荷的条件下，所述位单元的读取晶体管被移位到小于读取晶体管的阈值电压的第一电压，并且在 由所述位单元的电荷存储元件存储第二电荷，移位到等于或大于读取晶体管的阈值电压的第二电压，以及形成在所述半导体器件层中的多个增益晶体管，每个 增益晶体管经由连接到所述相应位堆栈的每个位单元的读晶体管的读出线连接到所述位堆栈中的相应一个，并适于输出放大的读数据 ut信号。

公开(公告)号：EP4019462A1

公开(公告)日：2022-06-29

申请号：EP20216325.9

申请日：2020-12-22

申请人： IMEC VZW

发明人： RYCKAERT, Julien ,  HORIGUCHI, Naoto ,  CHAN, Boon Teik

IPC分类号： B82Y10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/08

摘要： According to an aspect there is provided a FET device, in particular a Forksheet device. The FET device comprises a common source body portion (122) and a set of source layer prongs (124) protruding therefrom in a first lateral direction. First dielectric layer portions (126) are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion (132) and a set of drain layer prongs (134) protruding in the first lateral direction. Second dielectric layer portions (136) are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion (142) and a set of gate prongs (144) protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong (144) is formed intermediate a respective pair of said first and second dielectric layer portions (126, 136). The device further comprises a channel region comprising a set of stacked channel layer portions (112). Each channel layer portion extends between a respective pair of source and drain layer prongs (124, 134). The channel layer portions (112) are arranged in spaces between the gate prongs (144). There is also provided a method for forming a FET device.