公开(公告)号：EP2559062B1

公开(公告)日：2015-11-04

申请号：EP11769730.0

申请日：2011-04-15

申请人： Intel Corporation

发明人： NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

IPC分类号： H01L21/60 ,  H01L23/48

CPC分类号： H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

公开(公告)号：EP2559062A2

公开(公告)日：2013-02-20

申请号：EP11769730.0

申请日：2011-04-15

申请人： Intel Corporation

发明人： NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

IPC分类号： H01L21/60 ,  H01L23/48

CPC分类号： H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

公开(公告)号：EP2548225A2

公开(公告)日：2013-01-23

申请号：EP11756940.0

申请日：2011-03-16

申请人： Intel Corporation

发明人： GUZEK, John, S. ,  NAIR, Vijay

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L23/14

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

公开(公告)号：EP2999318B1

公开(公告)日：2020-09-30

申请号：EP15186947.6

申请日：2011-04-15

申请人： Intel Corporation

发明人： NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

IPC分类号： H05K3/46 ,  H01L23/552 ,  H01L23/64 ,  H01L25/16 ,  H01L23/00 ,  H05K1/18 ,  H01L21/56

公开(公告)号：EP2548225B1

公开(公告)日：2018-02-28

申请号：EP11756940.0

申请日：2011-03-16

申请人： Intel Corporation

发明人： GUZEK, John, S. ,  NAIR, Vijay

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L23/14

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

公开(公告)号：EP2999318A1

公开(公告)日：2016-03-23

申请号：EP15186947.6

申请日：2011-04-15

申请人： Intel Corporation

发明人： NALLA, Ravi, K. ,  AZIMI, Hamid, R. ,  GUZEK, John, S. ,  GONZALEZ, Javier Soto ,  DELANEY, Drew, W.

IPC分类号： H05K3/44

摘要： A structure comprising: a die embedded in a coreless substrate, a dielectric material adjacent the die, die pad interconnect structures disposed in a die pad area of the die, and at least one functionalized carrier structure disposed within the coreless substrate, wherein a top surface of the at least one functionalized carrier structure is coplanar with a top surface of the coreless substrate.

摘要翻译： 一种结构，包括：嵌入在无芯基板中的管芯，与管芯相邻的电介质材料，设置在管芯的管芯焊盘区域中的管芯焊盘互连结构以及设置在无芯基板内的至少一个功能化载体结构， 所述至少一个官能化载体结构与所述无芯基板的顶表面共面。