公开(公告)号：EP1955366A1

公开(公告)日：2008-08-13

申请号：EP06837855.3

申请日：2006-11-17

申请人： Intel Corporation

发明人： BRASK, Justin, K. ,  DATTA, Suman ,  DOCZY, Mark, L. ,  BLACKWELL, James, M. ,  METZ, Matthew, V. ,  KAVALIEROS, Jack, T. ,  CHAU, Robert, S.

IPC分类号： H01L21/314 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L21/314 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7784

摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

公开(公告)号：EP3394900A1

公开(公告)日：2018-10-31

申请号：EP15911569.0

申请日：2015-12-24

申请人： INTEL Corporation

发明人： DEWEY, Gilbert, W. ,  AGRAWAL, Ashish ,  CHU-KUNG, Benjamin ,  LE, Van, H. ,  METZ, Matthew, V. ,  RACHMADY, Willy ,  KAVALIEROS, Jack, T. ,  RIOS, Rafael

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/517 ,  H01L29/785

摘要： Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：EP1700338A1

公开(公告)日：2006-09-13

申请号：EP04815333.2

申请日：2004-12-21

申请人： INTEL CORPORATION

发明人： KAVALIEROS, Jack ,  BRASK, Justin, K. ,  DOCZY, Mark, L. ,  HARELAND, Scott, A. ,  METZ, Matthew, V. ,  BARNS, Chris, E. ,  CHAU, Robert, S.

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

公开(公告)号：EP3123497A1

公开(公告)日：2017-02-01

申请号：EP14886790.6

申请日：2014-03-28

申请人： Intel Corporation

发明人： METZ, Matthew, V. ,  KAVALIEROS, Jack, T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  CHU-KUNG, Benjamin ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  PILLARISETTY, Ravi ,  CHAU, Robert, S.

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

摘要： An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

摘要翻译： 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一个实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 其他实施例包括在本文中。

公开(公告)号：EP1700338B1

公开(公告)日：2014-09-17

申请号：EP04815333.2

申请日：2004-12-21

申请人： Intel Corporation

发明人： KAVALIEROS, Jack ,  BRASK, Justin, K. ,  DOCZY, Mark, L. ,  HARELAND, Scott, A. ,  METZ, Matthew, V. ,  BARNS, Chris, E. ,  CHAU, Robert, S.

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

公开(公告)号：EP1955366B1

公开(公告)日：2011-08-24

申请号：EP06837855.3

申请日：2006-11-17

申请人： Intel Corporation

发明人： BRASK, Justin, K. ,  DATTA, Suman ,  DOCZY, Mark, L. ,  BLACKWELL, James, M. ,  METZ, Matthew, V. ,  KAVALIEROS, Jack, T. ,  CHAU, Robert, S.

IPC分类号： H01L21/314 ,  H01L21/28 ,  H01L21/335 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778 ,  H01L21/316 ,  H01L29/20

CPC分类号： H01L21/314 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28008 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/31645 ,  H01L29/2003 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7784

摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.