公开(公告)号：EP3179515A1

公开(公告)日：2017-06-14

申请号：EP15199187.4

申请日：2015-12-10

申请人： Nexperia B.V.

发明人： Donkers, Johannes Josephus Theodorus Marinus ,  Hurkx, Godefridus Adrianus Maria ,  Croon, Jeroen Antoon ,  Gajda, Mark Andrzej ,  Sonsky, Jan

IPC分类号： H01L29/778 ,  H01L29/872 ,  H01L21/338 ,  H01L21/329 ,  H01L23/29 ,  H01L29/40 ,  H01L29/20

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

摘要： A semiconductor device and a method of making the same. The device includes a substrate including an AlGaN layer (112) located on a GaN layer (106) for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers (110, 120) located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.

摘要翻译： 一种半导体器件及其制造方法。 该器件包括衬底，衬底包括位于GaN层（106）上的AlGaN层（112），用于在AlGaN层和GaN层之间的界面处形成二维电子气。 该器件还包括位于衬底主表面上的多个电触点。 该器件还包括位于衬底的主表面上的多个钝化层（110,120）。 多个钝化层包括接触主表面的第一区域的第一钝化材料的第一钝化层和接触主表面的第二区域的第二钝化材料的第二钝化层。 第一和第二钝化材料是不同的钝化材料。 不同的钝化材料可以是包含不同比例的硅的氮化硅组合物。

公开(公告)号：EP3193449B1

公开(公告)日：2020-03-11

申请号：EP16151746.1

申请日：2016-01-18

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Wynne, Barry

IPC分类号： H03K17/0814 ,  H03K17/10 ,  H01L49/02

公开(公告)号：EP4451325A1

公开(公告)日：2024-10-23

申请号：EP24167890.3

申请日：2024-03-29

申请人： Nexperia B.V.

发明人： Patel, Hamza Hanif ,  Yogeswaran, Nivasan ,  Gajda, Mark Andrzej

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L29/06 ,  H01L23/29 ,  H01L23/482

摘要： A method of manufacturing a semiconductor device, such as a power MOSFET, comprising: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, wherein the passivation slot is at least partially positioned over the metal layer, and wherein the passivation slot divides the passivation layer into multiple regions, wherein each region experiences a reduced tensile stress σ SiNx as a result of the passivation slot.

公开(公告)号：EP3193364A1

公开(公告)日：2017-07-19

申请号：EP16151749.5

申请日：2016-01-18

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Wynne, Barry

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L49/02 ,  H01L29/8605 ,  H01L29/66 ,  H01L21/265 ,  H01L29/207

摘要： A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

摘要翻译： 一种半导体装置， III-V半导体材料的管芯; 集成在管芯中的电阻器元件，电阻器元件包括由管芯的III-V族半导体材料中的第一注入材料限定的轨道，所述轨道与围绕轨道的隔离区域基本上与管芯的其余部分电隔离 。

公开(公告)号：EP4439651A1

公开(公告)日：2024-10-02

申请号：EP23164898.1

申请日：2023-03-29

申请人： Nexperia B.V.

发明人： Patel, Hamza Hanif ,  Yogeswaran, Nivasan ,  Gajda, Mark Andrzej

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L29/06 ,  H01L23/29 ,  H01L23/482

CPC分类号： H01L23/562 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/4824 ,  H01L29/06

摘要： A method of manufacturing a semiconductor device, such as a power MOSFET, comprising: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, wherein the passivation slot is at least partially positioned over the metal layer, and wherein the passivation slot divides the passivation layer into multiple regions, wherein each region experiences a reduced tensile stress σSiNx as a result of the passivation slot.

公开(公告)号：EP3193364B1

公开(公告)日：2020-10-21

申请号：EP16151749.5

申请日：2016-01-18

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Wynne, Barry

IPC分类号： H01L21/8252 ,  H01L29/207 ,  H01L21/265 ,  H01L29/66 ,  H01L29/8605 ,  H01L49/02 ,  H01L27/06 ,  H01L29/32 ,  H01L21/76 ,  H01L21/761 ,  H01L29/205 ,  H01L23/00

公开(公告)号：EP3385981A1

公开(公告)日：2018-10-10

申请号：EP17164854.6

申请日：2017-04-04

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Pandey, Saurabh ,  Yandoc, Ricardo Lagmay ,  Lai, Yan

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/4825 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/48 ,  H01L2224/40137 ,  H01L2224/48245 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/30107

摘要： Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

公开(公告)号：EP3193449A1

公开(公告)日：2017-07-19

申请号：EP16151746.1

申请日：2016-01-18

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Wynne, Barry

IPC分类号： H03K17/0814 ,  H03K17/10

摘要： A semiconductor arrangement comprising; a normally-on transistor (101) having first and second main terminals and a control terminal, a normally-off transistor (105) having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection (112) between one of the main terminals of the normally-on transistor (101) and one of the main terminals of the normally-off transistor (105), a current-source arrangement (113) connected to a node (112) on the connection and configured to provide for control of the voltage at said node between the normally-on (101) and normally-off (105) transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor (101) formed therein and a second semiconductor die having the normally-off transistor (105) formed therein, the current-source arrangement (113) formed in the first and/or second semiconductor dies.

摘要翻译： 一种半导体装置， 具有第一和第二主端子和控制端子的常导通晶体管（101），具有第一和第二主端子和控制端子的常关晶体管（105），所述晶体管通过连接（112 ）在常开晶体管（101）的一个主端子和常关晶体管（105）的一个主端子之间，电流源装置（113）连接到连接点上的节点（112） 并且被配置为通过提供预定的电流来控制常开（101）和常关（105）晶体管之间的所述节点处的电压，其中半导体装置包括III-V半导体的第一半导体管芯 其中形成有常导通晶体管（101）的第一半导体管芯和其中形成有常关晶体管（105）的第二半导体管芯，电流源装置（113）形成在第一和/或第二半导体管芯中。