公开(公告)号：EP2294615A2

公开(公告)日：2011-03-16

申请号：EP09774134.2

申请日：2009-06-25

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  RADIGAN, Steven

IPC分类号： H01L27/10 ,  H01L27/102 ,  H01L27/24 ,  H01L21/033

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.

公开(公告)号：EP2277201A1

公开(公告)日：2011-01-26

申请号：EP09731080.9

申请日：2009-04-01

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E.

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/124 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1691

摘要： A method of making a memory device includes forming a first conductive electrode (28), forming an insulating structure (13) over the first conductive electrode, forming a resistivity switching element (14) on a sidewall of the insulating structure, forming a second conductive electrode (26) over the resistivity switching element, and forming a steering element (22) in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.

公开(公告)号：EP1825475B1

公开(公告)日：2011-01-19

申请号：EP05852375.4

申请日：2005-11-29

申请人： Sandisk 3D LLC

发明人： SO, Kenneth, K. ,  FASOLI, Luca, G. ,  SCHEUERLEIN, Roy, E.

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677

摘要： An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

公开(公告)号：EP1929525B1

公开(公告)日：2010-12-22

申请号：EP06815745.2

申请日：2006-09-27

申请人： Sandisk 3D LLC

发明人： KUMAR, Tanmay ,  HERNER, Brad, S. ,  PETTI, Christopher, J. ,  SCHEUERLEIN, Roy, E.

IPC分类号： H01L27/10 ,  H01L27/24 ,  G11C11/56

CPC分类号： G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/165 ,  G11C2013/0073 ,  H01L27/101

摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

公开(公告)号：EP2227746A2

公开(公告)日：2010-09-15

申请号：EP08869429.4

申请日：2008-12-31

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  THAKUR, Randhir ,  MOORE, Chistopher

IPC分类号： G06F13/12 ,  G06F12/00 ,  G06F3/06 ,  G06F13/00

CPC分类号： G06F12/0638 ,  G06F11/1415 ,  G06F12/1425 ,  G06F2212/2142

摘要： Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-once storage sub-system memory device and a write-many storage sub-system memory device. Numerous other aspects are provided.

公开(公告)号：EP1938331A2

公开(公告)日：2008-07-02

申请号：EP06749086.2

申请日：2006-03-31

申请人： Sandisk 3D LLC

发明人： FASOLI, Luca, G. ,  SCHEUERLEIN, Roy, E.

IPC分类号： G11C15/02 ,  G11C8/00 ,  G11C5/06

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C7/18 ,  G11C29/808 ,  H01L27/101 ,  H01L27/105 ,  Y10T29/49002

摘要： An integrated circuit having a three-dimensional memory array provides for a given number of memory planes (FIG. 15), but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication mask for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuit for selectively enabling certain layer selector circuits is configurable (FIG. 33), and the layer selector circuits are suitably arranged , to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

公开(公告)号：EP2465116A1

公开(公告)日：2012-06-20

申请号：EP10744637.9

申请日：2010-08-06

申请人： Sandisk 3D LLC

发明人： YAN, Thomas ,  FASOLI, Luca ,  SCHEUERLEIN, Roy, E.

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C13/00 ,  G11C16/02 ,  G11C16/24 ,  G11C17/06 ,  G11C17/18

CPC分类号： G11C7/18 ,  G11C13/004 ,  G11C16/24 ,  G11C2029/0411 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.

公开(公告)号：EP2415054A1

公开(公告)日：2012-02-08

申请号：EP10726351.9

申请日：2010-03-30

申请人： Sandisk 3d, Llc

发明人： SCHEUERLEIN, Roy, E.

IPC分类号： G11C13/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non- volatile storage apparatus includes a set of Y lines, a common X line, multiple data storage elements each of which is connected to the common X line, a dummy storage element connected to the common X line and a particular Y line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable of being in a first state or a second state. The dummy storage element is in a conductive state. The control circuitry provides control signals to the common X line and the set of Y lines to change a first data storage element of the multiple data storage elements from the first state to the second state by passing a current into the first data storage element from the particular Y line through the dummy storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.

公开(公告)号：EP2304732A1

公开(公告)日：2011-04-06

申请号：EP09771207.9

申请日：2009-06-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  FASOLI, Luca, G. ,  YAN, Tianhong

IPC分类号： G11C13/00 ,  G11C7/22

CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

公开(公告)号：EP2304730A1

公开(公告)日：2011-04-06

申请号：EP09771201.2

申请日：2009-06-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  YAN, Tianhong

IPC分类号： G11C13/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3481 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.