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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
    1.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
    半导体器件及其制造方法

    公开(公告)号：EP3301723A1

    公开(公告)日：2018-04-04

    申请号：EP17188981.9

    申请日：2017-09-01

    申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

    发明人： ZHOU, Ming

    IPC分类号： H01L29/66 ,  H01L29/786

    摘要： The present invention relates to the technical field of semiconductor processes and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate containing a first dielectric layer; forming a lower gate material layer on the first dielectric layer; patterning the lower gate material layer to form gate lines; depositing a second dielectric layer to cover the gate lines; planarizing the second dielectric layer; forming an insulating buffer material layer; patterning the insulating buffer material layer to form a patterned insulating buffer layer containing multiple separate portions, each separate portion extending to intersect one or more gate lines; selectively growing a graphene layer on the patterned insulating buffer layer; forming a third dielectric layer to cover the graphene layer and the second dielectric layer; and forming an upper gate electrode layer on the third dielectric layer. In the present invention, a patterned graphene layer may be obtained by means of the selective growth of graphene, thereby avoiding undesired effects from patterning the graphene. In addition, the semiconductor device of the present invention may use a dual-gate structure that can offer better current control.

    摘要翻译： 本发明涉及半导体工艺技术领域，并且公开了一种半导体器件及其制造方法。 该方法包括：提供包含第一介电层的衬底; 在第一介电层上形成下栅极材料层; 图案化所述下栅极材料层以形成栅极线; 沉积第二介电层以覆盖栅极线; 平坦化第二介电层; 形成绝缘缓冲材料层; 图案化所述绝缘缓冲材料层以形成包含多个分离部分的图案化绝缘缓冲层，每个分离部分延伸以与一条或多条栅极线相交; 在图案化的绝缘缓冲层上选择性地生长石墨烯层; 形成第三介电层以覆盖石墨烯层和第二介电层; 以及在第三电介质层上形成上栅电极层。 在本发明中，图案化的石墨烯层可以通过石墨烯的选择性生长来获得，从而避免了图案化石墨烯的不利影响。 另外，本发明的半导体器件可以使用可以提供更好的电流控制的双栅极结构。

    METHOD FOR FABRICATING FINFET STRUCTURE
    3.
    发明公开
    METHOD FOR FABRICATING FINFET STRUCTURE 审中-公开
    制造FINFET结构的方法

    公开(公告)号：EP3226302A1

    公开(公告)日：2017-10-04

    申请号：EP17162505.6

    申请日：2017-03-23

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： ZHOU, Ming

    IPC分类号： H01L29/66 ,  H01L21/764

    CPC分类号： H01L29/785 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66795

    摘要： A method of forming a semiconductor device includes providing a substrate structure having a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer and a hard mask layer on top of the semiconductor layer. The method also includes forming a spacer layer on sidewalls of the fin structure. Next, using the hard mask layer and the spacer layer as a mask, the semiconductor substrate is etched to form recesses on both sides of the fin structure that extend partially to underneath the bottom of the fin structure. The method further includes forming a filler material to fill at least the recesses, thereby forming the first filler layer. The first filler layer may be oxidized to form a porous oxide layer and the remaining portion of the substrate under the fin structures may be oxidized to form an oxide layer.

    摘要翻译： 形成半导体器件的方法包括在半导体衬底上提供具有半导体衬底和鳍状结构的衬底结构。 鳍结构包括半导体层和半导体层上的硬掩模层。 该方法还包括在鳍结构的侧壁上形成间隔层。 接下来，使用硬掩模层和间隔层作为掩模，对半导体衬底进行蚀刻以在鳍结构的两侧上形成部分延伸到鳍结构的底部下方的凹部。 该方法还包括形成填充材料以填充至少凹槽，从而形成第一填充层。 第一填充物层可以被氧化以形成多孔氧化物层，并且鳍结构下方的衬底的其余部分可以被氧化以形成氧化物层。

    TOP-DOWN METHOD FOR FABRICATING NANOWIRE DEVICE
    4.
    发明公开
    TOP-DOWN METHOD FOR FABRICATING NANOWIRE DEVICE 审中-公开
    自上而下制造纳米线装置的方法

    公开(公告)号：EP3301073A1

    公开(公告)日：2018-04-04

    申请号：EP17192411.1

    申请日：2017-09-21

    申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

    发明人： ZHOU, Ming

    IPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3247 ,  H01L21/67069 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/786

    摘要： A method for manufacturing a semiconductor device includes providing a semiconductor substrate (201), performing an etch process on the semiconductor substrate to form a fin (2011) and a trench on opposite sides of the fin, forming an etch guide layer (204), preferably made of silicon oxide, filling the trench, performing an etch process on the etch guide layer to expose a first portion of the fin (20111), and selectively etching the exposed first portion of the fin to remove a portion of the exposed portion of the fin adjacent to an upper first surface of the etch guide layer to form a first nanowire (211). The method further includes repeating the etch process and the selectively etching process to sequentially form second and third nanowires (212, 213), and forming a gate structure (220) surrounding the nanowire. The first, second, and third nanowires are formed in the direction perpendicular to the semiconductor substrate.

    摘要翻译： 一种用于制造半导体器件的方法包括：提供半导体衬底（201），在半导体衬底上执行蚀刻工艺以在鳍的相对侧上形成鳍（2011）和沟槽，形成蚀刻引导层（204） 优选地由氧化硅制成，填充沟槽，在蚀刻引导层上执行蚀刻工艺以暴露鳍状物（20111）的第一部分，并且选择性地蚀刻鳍状物的暴露的第一部分以去除暴露的部分的 所述鳍状物邻近所述蚀刻引导层的上部第一表面以形成第一纳米线（211）。 该方法进一步包括重复蚀刻工艺和选择性蚀刻工艺以顺序地形成第二和第三纳米线（212,213），并且形成围绕纳米线的栅极结构（220）。 第一，第二和第三纳米线沿垂直于半导体衬底的方向形成。

    METHOD FOR FABRICATING CU INTERCONNECTION USING GRAPHENE
    5.
    发明公开
    METHOD FOR FABRICATING CU INTERCONNECTION USING GRAPHENE 审中-公开
    使用石墨烯制造铜互连的方法

    公开(公告)号：EP3279931A1

    公开(公告)日：2018-02-07

    申请号：EP17183708.1

    申请日：2017-07-28

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： ZHOU, Ming

    IPC分类号： H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/53238 ,  H01L21/32055 ,  H01L21/76805 ,  H01L21/76813 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/5329

    摘要： A method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line formed in the first dielectric layer and extending through to a surface of the substrate; removing a portion of the first dielectric layer on opposite sides of the metal interconnect line to expose a surface of the metal interconnect line and to form a recess; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer. The interconnect structure can prevent metal atoms of the metal interconnect line from diffusion into the first and second dielectric layers.

    摘要翻译： 一种用于制造互连结构的方法包括：提供衬底结构，该衬底结构包括衬底，衬底上的第一介电层以及形成在第一介电层中并延伸至衬底表面的金属互连线; 去除所述金属互连线的相对侧上的所述第一介电层的一部分以暴露所述金属互连线的表面并形成凹槽; 在金属互连线的暴露表面上形成石墨烯层; 以及形成填充凹槽并覆盖石墨烯层的第二介电层。 互连结构可以防止金属互连线的金属原子扩散到第一和第二电介质层中。

    METHOD AND DEVICE FOR FINFET WITH GRAPHENE NANORIBBON
    6.
    发明公开
    METHOD AND DEVICE FOR FINFET WITH GRAPHENE NANORIBBON 审中-公开
    具有石墨纳米带的鳍式场效应晶体管的方法和器件

    公开(公告)号：EP3264472A1

    公开(公告)日：2018-01-03

    申请号：EP17178739.3

    申请日：2017-06-29

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： ZHOU, Ming

    IPC分类号： H01L29/66 ,  H01L29/78

    摘要： A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

    摘要翻译： 一种用于形成半导体器件的方法包括提供衬底结构，该衬底结构在衬底上具有半导体衬底和半导体鳍片。 该方法还包括形成覆盖半导体鳍的催化材料层，并且在半导体鳍的下部中形成覆盖催化材料层的隔离区。 接下来，在半导体鳍状物的上部的催化材料层上形成石墨烯纳米带，并且在石墨烯纳米带上形成栅极结构。